參數(shù)資料
型號: MAX1192ETI+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/27頁
文件大?。?/td> 0K
描述: IC ADC 8BIT 22MSPS DL 28-TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 8
采樣率(每秒): 22M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,雙極;2 個差分,雙極
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
______________________________________________________________________________________
17
values originally held on C2a and C2b. These values
are then presented to the first stage quantizers and iso-
late the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the MAX1192
to track and sample/hold analog inputs of high frequen-
cies (>Nyquist). Both ADC inputs (INA+, INB+, INA-,
and INB-) can be driven either differentially or single
ended. Match the impedance of INA+ and INA-, as well
as INB+ and INB-, and set the common-mode voltage
to midsupply (VDD/2) for optimum performance.
Analog Inputs and Reference
Configurations
The MAX1192 full-scale analog input range is ±VREF
with a common-mode input range of VDD/2 ±0.2V. VREF
is the difference between VREFP and VREFN. The
MAX1192 provides three modes of reference operation.
The voltage at REFIN (VREFIN) sets the reference oper-
ation mode (Table 1).
In internal reference mode, connect REFIN to VDD or
leave REFIN unconnected. VREF is internally generated
to be 0.512V ±3%. COM, REFP, and REFN are low-
impedance outputs with VCOM = VDD/2, VREFP = VDD/2
+ VREF/2, and VREFN = VDD/2 - VREF/2. Bypass REFP,
REFN, and COM each with a 0.33F capacitor.
In buffered external reference mode, apply a 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with VCOM = VDD/2, VREFP =
VDD/2 + VREFIN/4, and VREFN = VDD/2 - VREFIN/4.
Bypass REFP, REFN, and COM each with a 0.33F
capacitor. Bypass REFIN to GND with a 0.1F capacitor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for COM, REFP, and REFN. With their buffers shut
down, these nodes become high-impedance inputs
(Figure 4) and can be driven through separate, external
reference sources. Drive VCOM to VDD/2 ±10%, drive
VREFP to (VDD/2 +0.256V) ±10%, and drive VREFN to
(VDD/2 - 0.256V) ±10%. Bypass REFP, REFN, and COM
each with a 0.33F capacitor.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the
Applications Information section.
Clock Input (CLK)
CLK accepts a CMOS-compatible signal level. Since
the interstage conversion of the device depends on the
repeatability of the rising and falling edges of the exter-
nal clock, use a clock with low jitter and fast rise and
fall times (<2ns). In particular, sampling occurs on the
rising edge of the clock signal, requiring this edge to
Figure 4. Unbuffered External Reference Mode Impedance
VREFIN
REFERENCE MODE
>0.8 x VDD
Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM
each with a 0.33F capacitor.
1.024V ±10%
Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to
REFIN. VREF is internally generated to be VREFIN/2. Bypass REFP, REFN, and COM each with a
0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor.
<0.3V
Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference
sources. VREF is the difference between the externally applied VREFP and VREFN. Bypass REFP,
REFN, and COM each with a 0.33F capacitor.
Table 1. Reference Modes
MAX1192
1.5V
1.25V
1.75V
62.5
μA
0
μA
COM
REFN
REFP
4k
Ω
4k
Ω
62.5
μA
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