M
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________
5
Note 1:
Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 2:
REFP, REFN, and COM should be bypassed to GND with a 0.1μF (min) or 1μF (typ) capacitor.
Note 3:
Digital outputs settle to V
IH
, V
IL
. Parameter guaranteed by design.
Note 4:
With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5:
Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 6:
Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating, f
INA and B
= 20.01MHz at
-0.5dB FS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA and B
= 20.01MHz at -0.5dB
FS; see
Typical Operating Characteristics
section, Digital Supply Current vs. Analog
Input Frequency
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA and B
= 20.01MHz at
-0.5dB FS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Offset, V
DD
±
5%
Gain, V
DD
±
5%
149
185
3
1
mA
Analog Supply Current
I
VDD
15
μA
16
mA
100
2
Output Supply Current
I
OVDD
10
μA
492
611
mW
10
3.3
±
3.4
±
0.81
mW
μW
mV/V
%/V
Analog Power Dissipation
PDISS
50
Power-Supply Rejection Ratio
PSRR
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
OE
Fall to Output Enable Time
OE
Rise to Output Disable Time
t
DO
C
L
= 20pF (Note 3)
4.8
7.4
ns
t
ENABLE
t
DISABLE
4.7
1.2
ns
ns
CLK Pulse Width High
t
CH
Clock period: 8.34ns; see
Typical Operating
Characteristics
section,
AC Performance vs.
Clock Duty Cycle
Clock period: 8.34ns; see
Typical Operating
Characteristics
section,
AC Performance vs.
Clock Duty Cycle
Wake up from sleep mode (Note 4)
Wake up from shutdown mode (Note 4)
4.17
ns
CLK Pulse Width Low
t
CL
4.17
ns
0.65
1.2
Wake-Up Time
t
WAKE
μs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
f
INA or B
= 20.01MHz at -0.5dB FS
f
INA or B
= 20.01MHz at -0.5dB FS (Note 5)
f
INA or B
= 20.01MHz at -0.5dB FS (Note 6)
-71
0.08
0.8
dBc
dB
Degrees
±
0.2
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V; OV
DD
= 2V; 0.1μF and 1.0μF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10k
resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted;
≥
+25
°
C guaranteed by production test, <+25
°
C guaranteed by design and characterization;
typical values are at T
A
= +25
°
C.)
