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參數(shù)資料
| 型號： | MAX1185 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs |
| 中文描述： | 雙路、10位、20Msps、+3V、低功耗ADC，內(nèi)置電壓基準(zhǔn)及復(fù)用并行輸出 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 495K |
| 代理商： | MAX1185 |
M
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3V, OV
DD
= +2.5V, 0.1μF and 1.0μF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10k
resistor, V
IN
= 2Vp-p (differential w.r.t. COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 20MHz,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
V
DD
OV
DD
2.7
1.7
3.0
2.5
35
2.8
1
3.6
3.6
50
V
V
Operating, f
INA or B
= 7.5MHz at -0.5dB FS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, C
L
= 15pF, f
INA or B
= 7.5MHz at
-0.5dB FS
mA
Analog Supply Current
I
VDD
15
μA
4
mA
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA or B
= 7.5MHz at -0.5dB FS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Offset
Gain
100
2
105
8.4
3
±
0.2
±
0.1
Output Supply Current
I
OVDD
10
150
μA
mW
Power Dissipation
PDISS
45
μW
mV/V
%/V
Power-Supply Rejection Ratio
PSRR
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
CLK Fall to CHB Output Data
Valid
t
DOA
Figure 3 (Note 3)
5
8
ns
t
DOB
Figure 3 (Note 3)
5
8
ns
Clock Rise/Fall to A/B Rise/Fall
Time
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
t
DA/B
6
ns
t
ENABLE
t
DISABLE
t
CH
t
CL
Figure 4
Figure 4
Figure 3, clock period: 50ns
Figure 3, clock period: 50ns
Wakeup from sleep mode (Note 4)
Wakeup from shutdown (Note 4)
10
1.5
ns
ns
ns
ns
25
±
7.5
25
±
7.5
0.51
1.5
Wake-Up Time
t
WAKE
μs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
f
INA or B
= 7.5MHz at -0.5dB FS
f
INA or B
= 7.5MHz at -0.5dB FS
f
INA or B
= 7.5MHz at -0.5dB FS
-70
0.02
0.25
dB
dB
±
0.2
d eg ees
Note 1:
SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale
input voltage range.
Note 2:
Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 3:
Digital outputs settle to V
IH
, V
IL
. Parameter guaranteed by design.
Note 4:
With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5:
Equivalent dynamic performance is obtainable over full OV
DD
range with reduced C
L
.
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