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參數資料
| 型號： | MAX1182ECM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 2/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 65MSPS DUAL 48-TQFP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 250 |
| 位數： | 10 |
| 采樣率（每秒）： | 65M |
| 數據接口： | 并聯(lián) |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 240mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應商設備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 托盤 |
| 輸入數目和類型： | 4 個單端，雙極；2 個差分，雙極 |
| 產品目錄頁面： | 1396 (CN2011-ZH PDF) |
MAX1182
Dual 10-Bit, 65Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
10
______________________________________________________________________________________
Pin Description (continued)
PIN
NAME
FUNCTION
21
D9B
Three-State Digital Output, Bit 9 (MSB), Channel B
22
D8B
Three-State Digital Output, Bit 8, Channel B
23
D7B
Three-State Digital Output, Bit 7, Channel B
24
D6B
Three-State Digital Output, Bit 6, Channel B
25
D5B
Three-State Digital Output, Bit 5, Channel B
26
D4B
Three-State Digital Output, Bit 4, Channel B
27
D3B
Three-State Digital Output, Bit 3, Channel B
28
D2B
Three-State Digital Output, Bit 2, Channel B
29
D1B
Three-State Digital Output, Bit 1, Channel B
30
D0B
Three-State Digital Output, Bit 0 (LSB), Channel B
31, 34
OGND
Output Driver Ground
32, 33
OVDD
Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1F capacitor.
Output driver supply accepts a 1.7V to 3.6V input range.
35
D0A
Three-State Digital Output, Bit 0 (LSB), Channel A
36
D1A
Three-State Digital Output, Bit 1, Channel A
37
D2A
Three-State Digital Output, Bit 2, Channel A
38
D3A
Three-State Digital Output, Bit 3, Channel A
39
D4A
Three-State Digital Output, Bit 4, Channel A
40
D5A
Three-State Digital Output, Bit 5, Channel A
41
D6A
Three-State Digital Output, Bit 6, Channel A
42
D7A
Three-State Digital Output, Bit 7, Channel A
43
D8A
Three-State Digital Output, Bit 8, Channel A
44
D9A
Three-State Digital Output, Bit 9 (MSB), Channel A
45
REFOUT
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor
divider.
46
REFIN
Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a > 1nF capacitor.
47
REFP
Positive Reference Input/Output. Conversion range is
± (VREFP - VREFN). Bypass to GND with a
> 0.1F capacitor.
48
REFN
Negative Reference Input/Output. Conversion range is
± (VREFP - VREFN). Bypass to GND with
a > 0.1F capacitor.
—
EP
Exposed Paddle. Connect to analog ground.
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