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參數(shù)資料
| 型號(hào)： | MAX1180ECM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs |
| 中文描述： | 2-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, MS-026ABA-HD, TQFP-48 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 573K |
| 代理商： | MAX1180ECM |
M
Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
14
______________________________________________________________________________________
SNR
dB
= 20
log
10
(1 / [2
π
x f
IN
t
AJ
]),
where f
IN
represents the analog input frequency and
t
AJ
is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1180 clock input operates with a voltage thresh-
old set to V
DD
/2. Clock inputs with a duty cycle other
than 50%, must meet the specifications for high and low
periods as stated in the
Electrical Characteristics.
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1180
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 4 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (
OE
)
All digital outputs, D0A
–
D9A (Channel A) and D0B
–
D9B
(Channel B), are TTL/CMOS logic-compatible. There is
a five clock cycle latency between any particular sam-
ple and its corresponding output data. The output cod-
ing can be chosen to be either straight offset binary or
two
’
s complement (Table 1) controlled by a single pin
(T/B). Pull T/B low to select offset binary and high to
activate two
’
s complement output coding. The capaci-
tive load on the digital outputs D0A
–
D9A and D0B
–
D9B
should be kept as low as possible (<15pF), to avoid
large digital currents that could feed back into the ana-
log portion of the MAX1180, thereby degrading its
dynamic performance. Using buffers on the digital out-
puts of the ADCs can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1180 small-series
resistors (e.g., 100
), add to the digital output paths,
close to the MAX1180.
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wake-up and data output valid.
Power-Down (PD) and Sleep (SLEEP)
Modes
The MAX1180 offers two power-save modes, sleep and
full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled) and current consumption is reduced to
2.8mA.
To enter full power-down mode, pull PD high. With
OE
simultaneously low, all outputs are latched at the last
value prior to the power-down. Pulling
OE
high, forces
the digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
DD
/2 output voltage for level-
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers. The user
may select the R
ISO
and C
IN
values to optimize the filter
performance to suit a particular application. For the
application in Figure 5, a R
ISO
of 50
is placed before
the capacitive load to prevent ringing and oscillation.
The 22pF C
IN
capacitor acts as a small bypassing
capacitor.
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully-differential signal, required by the MAX1180 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V
DD
/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1180 provides better SFDR and
THD with fully-differential input signals, than a single-
ended drive, especially for high input frequencies. In
differential input mode, even-order harmonics are lower
as both inputs (INA+, INA- and/or INB+, INB-) are bal-
OUTPUT
D9A
–
D0A
OE
t
DISABLE
t
ENABLE
HIGH-Z
HIGH-Z
VALID DATA
OUTPUT
D9B
–
D0B
HIGH-Z
HIGH-Z
VALID DATA
Figure 4. Output Timing Diagram
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參數(shù)描述 |
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| MAX1180ECM+D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1180ECM+TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1180ECM-D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1180ECM-T | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
| MAX1180ECM-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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