Controllers with I2C/SP" />
參數(shù)資料
型號(hào): MAX11803EWC+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 27/59頁(yè)
文件大小: 0K
描述: IC TOUCH SCREEN CTLR 12-WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 電阻
觸摸面板接口: 4 線
輸入數(shù)/鍵: 1 TSC
分辨率(位): 12 b
數(shù)據(jù)接口: I²C,串行
數(shù)據(jù)速率/采樣率 (SPS,BPS): 105k
電源電壓: 1.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 12-WLP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX11803EWC+TDKR
MAX11800–MAX11803
Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I2C/SPI Interface
______________________________________________________________________________________
33
Delayed Touch Detection During Mode Transitions
The MAX11800/MAX11801 support a low-power power-
down mode suspending all touch-screen activity and
the panel is not driven. In this mode, the
MAX11800/MAX11801 is unable to detect a touch.
When commanded to transition from PWRDN to any
normal mode of operation, the MAX11800/MAX11801
go through a PUR/PUF sequence prior to observing the
panel touch status, minimizing the occurrence of inter-
rupts issued by false touches caused by the initial state
of panel capacitances.
In addition, when commanded to transition between
normal operating modes, the MAX11800/MAX11801
clear any existing interrupts and go through the
PUR/PUF sequence prior to observing the current panel
touch status.
FIFO Memory
The MAX11800/MAX11801 include an internal FIFO to
store scan block results for readback through the AP.
Each scan block result contains complete data for all
measurements requested by the scan type (X, Y; or X,
Y, Z1; or X, Y, Z1, Z2). The depth of each scan data
block ranges from 32 bits (X, Y mode) to 48 bits (X, Y,
Z1 mode) or 64 bits (X, Y, Z1, and Z2 mode).
The internal FIFO stores up to 16 complete scan
blocks, a total of 1024 bits. Regularly service the FIFO
to prevent overflow conditions. In the event of an over-
flow, the FIFO ceases to write new data until the old
data is read or cleared. Avoid overflow to prevent data
loss and unreliable behavior.
Check the general status register (0x00) and the FIFO
overflow bit to determine if the FIFO is in overflow. The
FIFO overflow bit asserts when a data overflow occurs.
See the
Clearing FIFO section.
Clearing FIFO
Write to the operating mode configuration register
(0x0B) to clear the FIFO. Modifying the contents of the
register is not necessary as any write operation to this
register location clears the FIFO and the interrupt TIRQ
(if present).
The FIFO completely clears when autonomous conver-
sions halt and the MAX11800/MAX11801 transition to
direct conversion mode. The FIFO also clears on transi-
tions from direct conversion mode to autonomous
mode.
FIFO Data Block Readback Structure
Table 10 illustrates the scan data block structure within
the FIFO for each scan type. Block boundaries are indi-
cated by bold lines. Numeric subscripts denote the
sample order when the data was taken. Readback pro-
ceeds from top to bottom. FIFO blocks are written as a
complete unit with an interrupt issued only after all
required block measurements are complete and data is
tagged. A FIFO data block consists of 2, 3, or 4 FIFO
data words (word = 16 bits).
2-WORD BLOCK
(X, Y)
3-WORD BLOCK
(X, Y, Z1)
4-WORD BLOCK
(X, Y, Z1, Z2)
X1 MSB
X1 LSB
Y1 MSB
Y1 LSB
X2 MSB
Z11 MSB
X2 LSB
Z11 LSB
Y2 MSB
X2 MSB
Z21 MSB
Y2 LSB
X2 LSB
Z21 LSB
X3 MSB
Y2 MSB
X2 MSB
X3 LSB
Y2 LSB
X2 LSB
Y3MSB
Z22 MSB
Y2 MSB
Y3 LSB
Z22 LSB
Y2 LSB
X4 MSB
.
Z12 MSB
X4 LSB
.
Z12 LSB
Y4 MSB
.
Z22 MSB
Y4 LSB
.
Z22 LSB
Table 10. FIFO Data Block Structure
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