Controllers with I2C/SP" />
參數(shù)資料
型號(hào): MAX11802EWC+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/59頁(yè)
文件大小: 0K
描述: IC TOUCH SCREEN CTLR 12-WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 電阻
觸摸面板接口: 4 線
輸入數(shù)/鍵: 1 TSC
分辨率(位): 12 b
數(shù)據(jù)接口: 串行,SPI?
數(shù)據(jù)速率/采樣率 (SPS,BPS): 105k
電源電壓: 1.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 12-WLP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX11802EWC+TDKR
MAX11800–MAX11803
Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I2C/SPI Interface
10
______________________________________________________________________________________
SPI TIMING CHARACTERISTICS
(VDD = 1.7V to 3.6V, TA = -40°C to +85°C (MAX11800E and MAX11802E), TA = -40°C to +105°C (MAX11800G), unless otherwise
noted. Typical values are at TA = +25°C and VDD = 3.3V, unless otherwise noted. See Figure 2.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLK Frequency
fCLK
25
MHz
CLK Period
tCP
40
ns
CLK Pulse-Width High
tCH
18
ns
CLK Pulse-Width Low
tCL
18
ns
CS Low to 1st CLK Rise Setup
tCSS0
18
ns
CS Low After 0th CLK Rise Hold
tCSH0
To prevent a 0th CLK read from being taken
as a 1st read in a free-running application
0ns
CS High to 17th CLK Setup
tCSS1
To prevent a 17th CLK read from being
recognized by the device in a free-running
application
18
ns
CS High After 16th CLK Falling
Edge Hold
tCSH1
0ns
CS Pulse-Width High
tCSW
18
ns
DIN to CLK Setup
tDS
25
ns
DIN Hold After CLK
tDH
0ns
DOUT Transition Valid After CLK
Rise
tDOT
Output transition time
25
ns
DOUT Remains Valid After CLK
Rise
tDOH
Output hold time
3
ns
DOUT Valid Before CLK Rise
tDO1
tDO1 = tCP - tDOT
10
ns
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
40
ns
CLK Rise to DOUT Enable
tDOE
CLOAD = 20pF. Minimum = hold time with
regard to 8th CLK read. Maximum =
transition time with regard to 8th CLK read.
325
ns
SDA
SCL
S
tF
tHD;STA
tLOW
tR
tHD;DAT
tSU;DAT
tHIGH
tF
tSU;STA
tHD;STA
Sr
tSP
tBUF
tSU;STO
P
S
Figure 1. I2C Timing Diagram
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