參數(shù)資料
型號(hào): MAX1177CEUP+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/13頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 135KSPS 20-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
采樣率(每秒): 135k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 879mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極
MAX1177
Reading the Conversion Result
EOC is provided to flag the P when a conversion is
complete. The falling edge of EOC signals that the data is
valid and ready to be output to the bus. D0–D15 are the
parallel outputs of the MAX1177. These tri-state outputs
allow for direct connection to a microcontroller I/O bus.
The outputs remain high impedance during acquisition
and conversion. Data is loaded onto the output bus with
the third falling edge of CS with R/C high (after tDO).
Bringing CS high forces the output bus back to high
impedance. The MAX1177 then waits for the next falling
edge of CS to start the next conversion cycle (Figure 2).
HBEN toggles the output between the high/low byte. The
low byte is loaded onto the output bus when HBEN is
low, and the high byte is on the bus when HBEN is high.
Transfer Function
Figure 8 shows the MAX1177 output transfer function.
The output is coded in standard binary.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy and prevent loading the
source. When the input signal is multiplexed, switch the
channels immediately after acquisition, rather than near
the end of, or after, a conversion. This allows more time
for the input buffer amplifier to respond to a large step
change in input signal. The input amplifier must have a
high enough slew rate to complete the required output
voltage change before the beginning of the acquisition
time. Figure 9 shows an example of this circuit using
the MAX427.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do
not run analog and digital lines parallel to each other,
and do not lay out digital signal paths underneath the
ADC package. Use separate analog and digital ground
planes with only one point connecting the two ground
systems (analog and digital) as close to the device as
possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, isolate the digital and analog
supply by connecting them with a low-value (10
)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the
AVDD supply. Bypass AVDD to AGND with a 0.1F
capacitor in parallel with a 1F to 10F low-ESR capaci-
tor with the smallest capacitor closest to the device.
Keep capacitor leads short to minimize stray inductance.
16-Bit, 135ksps, Single-Supply ADC
with to 10V Input Range
10
______________________________________________________________________________________
OUTPUT CODE
FULL-SCALE
TRANSITION
1111 1111 1111 1111
0
FULL-SCALE RANGE (FSR) = +10V
INPUT VOLTAGE (LSB)
1 LSB =
1111 1111 1111 1110
1111 1111 1111 1101
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
INPUT RANGE = 0V TO +10V
2
1
3
65,535
65,534 65,536
FSR x VREF
65536 x 4.096
Figure 8. MAX1177 Transfer Function
MAX1177
MAX427
ANALOG
INPUT
AIN
Figure 9. MAX1177 Fast-Settling Input Buffer
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