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參數(shù)資料
| 型號： | MAX1172CDJ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 30Msps, TTL-Output ADC |
| 中文描述： | 1-CH 12-BIT FLASH/SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP32 |
| 封裝： | SIDEBRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 84K |
| 代理商： | MAX1172CDJ |
M
12-Bit, 30Msps, T T L-Output ADC
10
______________________________________________________________________________________
Analog Input
V
IN
is the analog input. The full-scale input range will be
80% of the reference voltage or ±2V with V
FB
= -2.5V
and V
FT
= +2.5V.
The drive requirements for the analog inputs are minimal
compared to those of conventional flash converters, due
to the MAX1172’s extremely low 5pF input capacitance
and high 300k
input impedance. For example, for an
input signal of ±2Vp-p with an input frequency of
10MHz, the peak output current required for the driving
circuit is only 628μA.
Cloc k Input
The MAX1172 is driven from a single-ended TTL input
(CLK). The clock pulse width (t
PWH
) must be kept
between 15ns and 300ns to ensure proper operation of
the internal track/hold amplifier (Figure 1a). When oper-
ating the MAX1172 at sampling rates above 3Msps, it is
recommended that the clock input duty cycle be kept
at 50% to optimize performance (Figure 4). The analog
input signal is latched on the rising edge of the CLK.
The clock input must be driven from fast TTL logic (V
IH
≤
4.5V, t
RISE
< 6ns). In the event the clock is driven
from a high current source, use a 100
(R1, Figure 2)
resistor in series to current limit to approximately 45mA.
Digital Outputs
The format of the output data (D0-D11) is straight bina-
ry (Table 2). The outputs are latched on the rising edge
of CLK with a typical propagation delay of 14ns. There
is a one clock cycle latency between CLK and the valid
output data (Figure 1a).
The digital outputs’ rise times and fall times are not
symmetrical. The rise time’s typical propagation delay
is 14ns, and the typical fall time is 6ns (Figure 5). The
nonsymmetrical rise and fall times create approximately
8ns of invalid data.
Table 2. Output Data Information
( indicates the flickering bit between logic 0 and 1).
Overrange Output
The overrange output (D12) is an indication that the an-
alog input signal has exceeded the full-scale input volt-
age by 1LSB. When this condition occurs, the outputs
will switch to logic 1s. All other data outputs are unaf-
fected by this operation. This feature makes it possible
to include the MAX1172 in higher resolution systems.
Evaluation Board
The MAX1170 evaluation kit (EV kit) is available to aid
designers in demonstrating the full performance of the
MAX1172 (or of the MAX1170/MAX1171). This board
includes a reference circuit, clock driver circuit, output
data latches, and on-board reconstruction of the digital
data. A separate EV kit manual describing the opera-
tion of this board is available. Contact the factory for
price and availability.
ANALOG
INPUT
> +2.0V + 1/2LSB
+2.0V - 1LSB
0.0V
-2.0V + 1LSB
< -2.0V
0
0
0
0
1
OVERRANGE
D10
OUTPUT CODE
D9–D0
11 1111 1111
11 1111 111
00 0000 000
00 0000 0000
Figure 4. Signal-to-Noise Ratio vs. Clock Duty Cycle
51
25
DUTY CYCLE OF POSITIVE CLOCK PULSE (%)
35
45
55
65
75
SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
55
53
M
S
59
57
63
65
67
61
P
P
t
PWL
DUTY CYCLE = t
PWH
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| MAX1174ACUP-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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