- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383311 > MAX1170CDJ (MAXIM INTEGRATED PRODUCTS INC) 12-Bit, 10Msps, TTL-Output ADC PDF資料下載
參數(shù)資料
| 型號： | MAX1170CDJ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 10Msps, TTL-Output ADC |
| 中文描述： | 1-CH 12-BIT FLASH/SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP32 |
| 封裝： | SIDEBRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 83K |
| 代理商： | MAX1170CDJ |
M
12-Bit, 10Msps, T T L-Output ADC
_______________________________________________________________________________________
9
AGND and DGND are the two grounds available on the
MAX1170. These two internal grounds are isolated on
the device. The use of ground planes is recommended
to achieve optimum device performance. DGND is
needed for the DV
CC
return path (40mA typical) and for
the return path for all digital output logic interfaces.
AGND and DGND should be separated from each
other and connected together only at the device
through a ferrite bead.
A Schottky or hot carrier diode connected between
AGND and V
EE
is required. The use of separate power
supplies between V
CC
and DV
CC
is not recommended
due to potential power-supply sequencing latchup con-
ditions. Use of the recommended interface circuit shown
in Figure 2 will provide optimum device performance for
the MAX1170.
V oltage Referenc e
The MAX1170 requires the use of two voltage refer-
ences: V
FT
and V
FB
. V
FT
is the force for the top of the
voltage reference ladder (+2.5V typical), V
FB
(-2.5V
typical) is the force for the bottom of the voltage refer-
ence ladder. Both voltages are applied across an inter-
nal reference ladder resistance of 800
. The +2.5V
voltage source for reference V
FT
must be current limit-
ed to 20mA maximum if a different driving circuit is
used in place of the recommended reference circuit
shown in Figures 2 and 3.
In addition, there are five reference ladder taps (V
ST
,
VR
T1
, VR
T2
, VR
T3
, and V
SB
). V
ST
is the sense for the
top of the reference ladder (+2.0V), VR
T2
is the mid-
point of the ladder (0.0V typical), and V
SB
is the sense
for the bottom of the reference ladder (-2.0V). VR
T1
and
VR
T3
are quarter-point ladder taps (+1.0V and -1.0V
typical, respectively). The voltages seen at V
ST
and
V
SB
are the true full-scale input voltages of the device
when V
FT
and V
FB
are driven to the recommended volt-
ages (+2.5V and -2.5V typical, respectively). V
ST
and
V
SB
can be used to monitor the actual full-scale input
voltage of the device. VR
T1
, VR
T2
, and VR
T3
should not
be driven to the expected ideal values, as is commonly
done with standard flash converters. A decoupling
capacitor of 0.01μF connected to AGND from each tap
is recommended to minimize high-frequency noise
injection.
The analog input range will scale proportionally with
respect to the reference voltage if a different input
range is required. The maximum scaling factor for
device operation is ±20% of the recommended refer-
ence voltages of V
FT
and V
FB
. However, because the
MAX1170 is laser trimmed to optimize performance
with ±2.5V references, its accuracy will degrade if
operated beyond a ±2% range.
An example of a recommended reference driver circuit
is shown in Figure 2. IC1 is REF-03, the +2.5V refer-
ence with a tolerance of 0.6% or ±0.015V. The 10k
potentiometer supports an adjustable range of 150mV.
IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1%
with good TC tracking to maintain a 0.3LSB matching
between V
FT
and V
FB
. If 0.1% matching is not met, then
potentiometer R4 can be used to adjust the V
FB
voltage
to the desired level. Adjust R1 and R4 such that V
ST
and V
SB
are exactly +2.0V and -2.0V, respectively.
The following errors are defined:
+FS error = top of ladder offset voltage
=
(+FS - V
ST
)
-FS error = bottom of ladder offset voltage
=
(-FS - V
SB
)
Where the +FS (full scale) input voltage is defined as
the output 1LSB above the transition of 1–10 and 1–11,
and the -FS input voltage is defined as the output 1LSB
below the transition of 0–00 and 0–01.
A
V
FT
V
IN
V
CC
V
EE
Figure 3. Analog Equivalent Input Circuit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX1177 | 16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range |
| MAX1177ACUP | 16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range |
| MAX1177AEUP | 16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range |
| MAX1177BCUP | 16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range |
| MAX1177BEUP | 16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1171CDJ | 制造商:Maxim Integrated Products 功能描述: |
| MAX1174ACUP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1174ACUP+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-Bit 135ksps 4.2V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1174ACUP+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-Bit 135ksps 4.2V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1174ACUP-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復。