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參數資料
| 型號： | MAX1170CBH |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 10Msps, TTL-Output ADC |
| 中文描述： | 1-CH 12-BIT FLASH/SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CQFP44 |
| 封裝： | MO-047AC, CERQUAD-44 |
| 文件頁數： | 10/12頁 |
| 文件大?。?/td> | 83K |
| 代理商： | MAX1170CBH |
M
12-Bit, 10Msps, T T L-Output ADC
10
______________________________________________________________________________________
Analog Input
V
IN
is the analog input. The full-scale input range will be
80% of the reference voltage or ±2V with V
FB
= -2.5V
and V
FT
= +2.5V.
The drive requirements for the analog inputs are minimal
compared to those of conventional flash converters, due
to the MAX1170’s extremely low 5pF input capacitance
and high 300k
input impedance. For example, for an
input signal of ±2Vp-p with an input frequency of
10MHz, the peak output current required for the driving
circuit is only 628μA.
Cloc k Input
The MAX1170 is driven from a single-ended TTL input
(CLK). For optimal noise performance, the clock input
slew rate should be a minimum of 6ns. Because of this,
the use of fast logic is recommended. The clock input
duty cycle should be 50% where possible, but perfor-
mance will not be degraded if kept within the range of
40% to 60%. However, in any case, the clock pulse
width (t
PWH
) must be kept at 300ns maximum to ensure
proper operation of the internal track/hold amplifier
(Figure 1a). The analog input signal is latched on the
rising edge of the CLK.
The clock input must be driven from fast TTL logic (V
IH
≤
4.5V, t
RISE
< 6ns). In the event the clock is driven from a
high current source, use a 100
resistor (R1, Figure 2)
in series to current limit to approximately 45mA.
Digital Outputs
The format of the output data (D0-D11) is straight bina-
ry (Table 2). The outputs are latched on the rising edge
of CLK with a typical propagation delay of 14ns. There
is a one clock cycle latency between CLK and the valid
output data (Figure 1a).
The digital outputs’ rise times and fall times are not
symmetrical. The rise time’s typical propagation delay
is 14ns, and the typical fall time is 6ns (Figure 4). The
nonsymmetrical rise and fall times create approximately
8ns of invalid data.
Table 2. Output Data Information
( indicates the flickering bit between logic 0 and 1).
INVALID
DATA
INVALID
DATA
INVALID
DATA
INVALID
DATA
2.4V
3.5V
2.4V
0.8V
(N - 2)
(N - 1)
N
N + 1
(N - 2)
(N - 1)
(N - 1)
(N)
6ns
typ
t
PD1
14ns typ
t
6ns
CLK IN
DATA OUT
(ACTUAL)
DATA OUT
(EQUIVALENT)
Figure 4. Digital Output Characteristics
ANALOG
INPUT
> +2.0V + 1/2LSB
+2.0V - 1LSB
0.0V
-2.0V + 1LSB
< -2.0V
0
0
0
0
1
OVERRANGE
D10
OUTPUT CODE
D9–D0
11 1111 1111
11 1111 111
00 0000 000
00 0000 0000
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相關代理商/技術參數 |
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| MAX1170CDJ | 制造商:Maxim Integrated Products 功能描述: |
| MAX1171CDJ | 制造商:Maxim Integrated Products 功能描述: |
| MAX1174ACUP | 功能描述:模數轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1174ACUP+ | 功能描述:模數轉換器 - ADC 14-Bit 135ksps 4.2V Precision ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1174ACUP+T | 功能描述:模數轉換器 - ADC 14-Bit 135ksps 4.2V Precision ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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