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參數(shù)資料
| 型號： | MAX1168BEEG |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters |
| 中文描述： | 8-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | QSOP-24 |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 462K |
| 代理商： | MAX1168BEEG |
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entire conversion result, 16 SCLK cycles are needed.
Extra clock pulses, occurring after the conversion result
has been clocked out and prior to the rising edge of
CS
, cause the conversion result to be shifted out again.
The MAX1167/MAX1168 internal clock 8-bit-wide data-
transfer mode requires 24 external clock cycles and 25
internal clock cycles for completion.
Force
CS
high after the conversion result is read. For
maximum throughput, force
CS
low again to initiate the
next conversion immediately after the specified mini-
mum time (t
CSW
). Forcing
CS
high in the middle of a
conversion immediately aborts the conversion and
places the MAX1167/MAX1168 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1167/MAX1168 in the internal clock mode. Enable
scanning by setting bits 4 and 3 in the command/con-
figuration/control register (see Tables 3 and 4). In scan
mode, conversion results are stored in memory until the
completion of the last conversion in the sequence.
Upon completion of the last conversion in the
sequence,
EOC
transitions from high to low to indicate
the end of the conversion and shuts down the internal
oscillator. Use the
EOC
high-to-low transition as the sig-
nal to restart the external clock (SCLK). DOUT provides
the conversion results in the same order as the channel
conversion process. The MSB of the first conversion is
available at DOUT on the falling edge of
EOC
(Figure 14).
M
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________
19
DOUT
CS
SCLK
DIN
EOC
X X X X X X X X
DATA
LSB
X
t
ACQ
X = DON,CONFIGURATION
DSPR = DSEL = DV
DD
t
CONV
POWER-DOWN
ADC
STATE
INTERNAL
CLK
1
8
9
16
2
13
32
24
17
32
MSB
Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
DOUT
CS
SCLK
DIN
EOC
ADC
STATE
INTERNAL
CLK
1
8
9
40
2
6
24
48
30
26
1
MSB
LSB
LSB
X
MSB
t
ACQ
X = CONFIGURATION
DSPR = DV
DD
, DSEL = GND (MAX1168 ONLY)
Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing
POWER-DOWN
t
CONV
t
ACQ
t
CONV
相關(guān)PDF資料 |
PDF描述 |
|---|---|
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1168BEEG+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 8Ch 200ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1168BEEG+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 8Ch 200ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1168BEEG+W | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| MAX1168BEEG-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1168CCEG | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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