參數(shù)資料
型號: MAX1168BEEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 19/30頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 200KSPS 24-QSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 16
采樣率(每秒): 200k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 762mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 24-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
26
______________________________________________________________________________________
DOUT*
CS
SCLK
1ST BYTE READ
2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
D1
D0
D7
D6
D5
D4
D3
D2
24
20
16
12
8
6
4
1
D15
D14
D13
D12
D11
D10
D9
D8
0
00
0
Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
Serial Interfaces
SPI and MICROWIRE Interfaces
When using the SPI (Figure 20a) or MICROWIRE (Figure
20b) interfaces, set CPOL = 0 and CPHA = 0. Drive CS
low to power on the MAX1167/MAX1168 before starting a
conversion (Figure 20c). Three consecutive 8-bit-wide
readings are necessary to obtain the entire 16-bit result
from the ADC. DOUT data transitions on the serial clock’s
falling edge. The first 8-bit-wide data stream contains all
leading zeros. The 2nd 8-bit-wide data stream contains
the MSB through D6. The 3rd 8-bit-wide data stream con-
tains D5 through D0 followed by S1 and S0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and
CPHA = 0, the MAX1167/MAX1168 support a maximum
fSCLK of 4.8MHz. Figure 21a shows the MAX1167/
MAX1168 connected to a QSPI master, and Figure 21b
shows the associated interface timing.
PIC16 with SSP Module and PIC17
Interface
The MAX1167/MAX1168 are compatible with a
PIC16/PIC17 controller (C), using the synchronous seri-
al-port (SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 22a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 7 and 8.
In SPI mode, the PIC16/PIC17 Cs allow 8 bits of data to
be synchronously transmitted and received simultane-
ously. Three consecutive 8-bit-wide readings (Figure
22b) are necessary to obtain the entire 16-bit result from
the ADC. DOUT data transitions on the serial clock’s
falling edge and is clocked into the C on SCLK’s rising
edge. The first 8-bit-wide data stream contains all zeros.
The 2nd 8-bit-wide data stream contains the MSB
through D6. The 3rd 8-bit-wide data stream contains bits
D5 through D0 followed by S1 and S0.
DSP
EXTERNAL
CLOCK
SCLK
DSPR
DSPX
DIN
DOUT
SCLK
TFS
RFS
DT
DR
FL1
CS
MAX1168
Figure 23. DSP Interface Connection
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