Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm " />
參數(shù)資料
型號(hào): MAX11647EUA+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 6/22頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT I2C 94.4KSPS 8UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
采樣率(每秒): 94.4k
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 362mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極;1 個(gè)差分,單極;1 個(gè)差分,雙極
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
14
______________________________________________________________________________________
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (Figure 7)
and a write bit (R/W = 0). If the address byte is success-
fully received, the MAX11646/MAX11647 (slave) issue
an acknowledge. The master then writes to the slave.
The slave recognizes the received byte as the setup
byte (Table 1) if the most significant bit (MSB) is 1. If the
MSB is 0, the slave recognizes that byte as the configu-
ration byte (Table 2). The master can write either 1 or 2
bytes to the slave in any order (setup byte then configu-
ration byte, configuration byte then setup byte, setup
byte or configuration byte only; see Figure 9). If the
slave receives a byte successfully, it issues an acknowl-
edge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS mode, a STOP condition returns the bus
into F/S mode (see the
HS Mode section).
B. 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS
A
71 1
W
SETUP OR
CONFIGURATION BYTE
SETUP OR
CONFIGURATION BYTE
8
P or Sr
1
A
1
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS
A
71 1
W
SETUP OR
CONFIGURATION BYTE
8
P or Sr
1
A
1
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
A
1
8
A. 1-BYTE WRITE CYCLE
NUMBER OF BITS
Figure 9. Write Cycle
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SEL2
SEL1
SEL0
CLK
BIP/UNI
RST
X
BIT
NAME
DESCRIPTION
7
REG
Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
6
SEL2
5
SEL1
4
SEL0
Three bits select the reference voltage (Table 6). Default to 000 at power-up.
3
CLK
1 = external clock, 0 = internal clock. Defaulted to 0 at power-up.
2
BIP/UNI
1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section).
1
RST
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
0
X
Don’t-care bit. This bit can be set to 1 or 0.
Table 1. Setup Byte Format
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