參數資料
型號: MAX11633EEG+T
廠商: Maxim Integrated Products
文件頁數: 8/22頁
文件大?。?/td> 0K
描述: ADC 12BIT 300KSPS 16CH 24-QSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數: 12
采樣率(每秒): 300k
數據接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數目: 1
功率耗散(最大): 762mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 24-QSOP
包裝: 帶卷 (TR)
輸入數目和類型: 16 個單端,單極
MAX11626–MAX11629/MAX11632/MAX11633
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
16
______________________________________________________________________________________
AVGON
NAVG1
NAVG0
FUNCTION
0
x
Performs one conversion for each requested result.
1
0
Performs four conversions and returns the average for each requested result.
1
0
1
Performs eight conversions and returns the average for each requested result.
1
0
Performs 16 conversions and returns the average for each requested result.
1
Performs 32 conversions and returns the average for each requested result.
NSCAN1
NSCAN0
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
0
Scans channel N and returns four results.
0
1
Scans channel N and returns eight results.
1
0
Scans channel N and returns 12 results.
1
Scans channel N and returns 16 results.
BIT NAME
BIT
FUNCTION
7 (MSB)
Set to 0 to select reset register.
6
Set to 0 to select reset register.
5
Set to 0 to select reset register.
4
Set to 1 to select reset register.
RESET
3
Set to 0 to reset all registers. Set to 1 to clear the FIFO only.
x
2
Reserved. Don’t care.
x
1
Reserved. Don’t care.
x
0 (LSB)
Reserved. Don’t care.
Table 5. Reset Register
BIT NAME
BIT
FUNCTION
7 (MSB)
Set to 0 to select averaging register.
6
Set to 0 to select averaging register.
5
Set to 1 to select averaging register.
AVGON
4
Set to 1 to turn averaging on. Set to 0 to turn averaging off.
NAVG1
3
Configures the number of conversions for single-channel scans.
NAVG0
2
Configures the number of conversions for single-channel scans.
NSCAN1
1
Single-channel scan count. (Scan mode 10 only.)
NSCAN0
0 (LSB)
Single-channel scan count. (Scan mode 10 only.)
Table 4. Averaging Register*
*See below for bit details.
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