參數(shù)資料
型號(hào): MAX1161ACWI
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: Low-Voltage Adjustable Precision Shunt Regulator 3-SOT-89 -40 to 85
中文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: 0.300 INCH, PLASTIC, MS-013AE, SOIC-28
文件頁(yè)數(shù): 8/8頁(yè)
文件大?。?/td> 78K
代理商: MAX1161ACWI
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8
___________________Maxim Integrated Produc ts, 120 S an Gabriel Drive, S unnyvale, CA 94086 (408) 737-7600
1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
M
10-Bit, 40Msps, T T L-Output ADC
Cloc k Input
The MAX1161 is driven from a single-ended TTL input
(CLK). The CLK pulse width (t
pwH
) must be kept
between 10ns and 300ns to ensure proper operation of
the internal track/hold amplifier (Figure 1a). When oper-
ating the MAX1161 at sampling rates above 3Msps, it is
recommended that the clock input duty cycle be kept
at 50% to optimize performance (Figure 4). The analog
input signal is latched on the rising edge of CLK.
The clock input must be driven from fast TTL logic (VIH
4.5V, t
RISE
<6ns). In the event the clock is driven from
a high current source, use a 100
resistor (R5) in
series to limit current to approximately 45mA.
Digital Outputs
The format of the output data (D0–D9) is straight binary
(Table 2). The outputs are latched on the rising edge of
CLK with a propagation delay typically at 14ns. There is
a one-clock-cycle latency between CLK and the valid
output data (Figure 1a).
The digital outputs’ rise and fall times are not symmetri-
cal. Typical propagation delay is 14ns for the rise time
and 6ns for the fall time (Figure 5). The nonsymmetrical
rise and fall times create approximately 8ns of invalid
data.
Overrange Output
The overrange output (D10) is an indication that the
analog input signal has exceeded the positive full-scale
input voltage by 1LSB. When this condition occurs, D10
will switch to logic 1. All other data outputs (D0–D9) will
remain at logic 1 as long as D10 remains at logic 1.
This feature makes it possible to include the MAX1161
in higher-resolution systems.
Evaluation Board
The MAX1160 EV kit is available to help designers
demonstrate the MAX1160 or MAX1161’s full perfor-
mance. This board includes a reference circuit, clock-
driver circuit, output data latches, and an on-board
reconstruction of the digital data. A separate data sheet
describing the operation of this board is also available.
Contact the factory for price and availability.
43
25
60 65 70 75
35 40
30
45 50 55
51
53
45
47
49
DUTY CYCLE OF POSITIVE CLOCK PULSE (°C)
S
57
59
55
t
pwH
t
pwL
DUTY CYCLE = t
pwH
t
pwL
ANALOG
INPUT
> +2V + 1/2LSB
+2V - 1LSB
0.0V
-2V + 1LSB
0
0
0
1
OVERRANGE
D10
OUTPUT CODE
D9–D0
11 1111 1111
11 1111 111
00 0000 000
< 2V
0
00 0000 0000
Table 2. Output Data Information
CLK IN
DATA
OUT
(ACTUAL)
2.4V
3.5V
2.4V
0.5V
0.8V
t
pd1
typ
6ns
N
N + 1
DATA OUT
(EQUIVALENT)
(N - 1)
N
(N - 1)
N
t
6ns
(N - 2)
(N - 2)
14ns typ
INVALID
DATA
INVALID
DATA
INVALID
DATA
INVALID
DATA
Figure 5. Digital Output Characteristics
(
indicates the flickering bit between logic 0 and 1.)
Figure 4. SNR vs. Clock Duty Cycle
相關(guān)PDF資料
PDF描述
MAX1161BCWI 10-Bit, 40Msps, TTL-Output ADC
MAX1162 Low-Voltage Adjustable Precision Shunt Regulator 3-SOT-89 -40 to 85
MAX1162ACUB Low-Voltage Adjustable Precision Shunt Regulator 3-SOT-23 -40 to 125
MAX1162AC_B Low-Voltage Adjustable Precision Shunt Regulator 3-SOT-23 -40 to 125
MAX1162AEUB Low-Voltage Adjustable Precision Shunt Regulator 3-SOT-23 -40 to 125
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