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參數(shù)資料
| 型號(hào)： | MAX1151AIZS |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 8-Bit, 750Msps Flash ADC |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP80 |
| 封裝： | MQUAD-80 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | MAX1151AIZS |
M
8-Bit, 750Msps Flash ADC
4
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
NAME
FUNCTION
1, 2, 3
D2B, D3B, D4B
Data Output Bank, Bits 2, 3, and 4
4, 5, 19, 20, 22, 23, 27, 28, 38, 39,
40, 46, 47, 49, 60, 67, 79
V
EE
Negative Supply, nominally -5.2V
PIN
6
D5B
Data Output Bank B, Bit 5
7, 9, 11, 54, 56, 58,
69, 71, 73, 75, 77
DGND
Digital Ground
13, 14, 31, 34, 41, 63, 64
N.C.
No Connection. Not internally connected.
12
D8B
Data Output Bank B, Bit 8 (OVR)
10
D7B
Data Output Bank B, Bit 7 (MSB)
8
D6B
Data Output Bank B, Bit 6
35
42
VRM
VRTF
Reference-Voltage Middle, nominally -1V
Reference-Voltage Force Top
32, 33
VIN
Analog Input Voltage. Can be either voltage or sense.
24
VRBS
Reference-Voltage Sense Bottom
21
VRBF
Reference-Voltage Force Bottom
15-18, 25, 26, 29, 30, 36,
37, 44, 45, 51, 52
AGND
Analog Ground
50
53
CLK
DRA
Clock Input
Data Ready Bank A
48
NCLK
Inverse Clock Input
43
VRTS
Reference-Voltage Sense Top
59, 61, 62, 65, 66, 68
70
D1A–D6A
D7A
Data Output Bank A, Bits 1–6
Data Output Bank A, Bit 7 (MSB)
57
D0A
Data Output Bank A, Bit 0 (LSB)
55
NDRA
Not Data Ready Bank A
72
74
D8A
NDRB
Data Output Bank A, Bit 8 (OVR)
Not Data Ready Bank B
80
D1B
Data Output Bank B, Bit 1
78
D0B
Data Output Bank B, Bit 0 (LSB)
76
DRB
Data Ready Bank B
_______________Detailed Desc ription
The MAX1151 is one of the fastest monolithic, 8-bit, paral-
lel, flash analog-to-digital converters (ADCs) available
today. The nominal conversion rate is 750Msps, and the
analog bandwidth is in excess of 900MHz. A major
advance over previous flash converters is the inclusion of
255 input preamplifiers between the reference ladder and
input comparators (see Functional Diagram. This not
only reduces clock transient kickback to the input and
reference ladder but also reduces the effect of the input
signal’s dynamic state on the input comparators’ latching
characteristics. The preamplifiers act as buffers to stabi-
lize the input capacitance so that it remains constant over
different input voltage and frequency ranges, making the
part easier to drive than previous flash converters. The
preamplifiers also add a gain of +2 to the input signal, so
that each comparator has a wider overdrive or threshold
range to trip into or out of the active state. This gain
reduces metastable states that can cause errors at the
output.
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