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參數(shù)資料
| 型號： | MAX1149BEUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 116KSPS 20-TSSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 116k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 879mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極 |
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________
13
Input Bandwidth
The MAX1146–MAX1149 feature input tracking circuitry
with a 3.0MHz small-signal bandwidth. The 3.0MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes clamp the analog input to
VDD and AGND. These diodes allow the analog inputs
to swing from (AGND - 0.3V) to (VDD + 0.3V) without
causing damage to the device. For accurate conver-
sions, the inputs must not go more than 50mV below
AGND or above VDD.
Note: If the analog input exceeds 50mV beyond the sup-
ply rails, limit the current to 2mA.
Quick Look
Use the circuit of Figure 7 to quickly evaluate the
MAX1148/MAX1149. The MAX1148/MAX1149 require a
control byte to be written to DIN using SCLK before
each conversion. Connecting DIN to VDD and clocking
SCLK feeds in a control byte of $FF HEX (see Table 1).
Trigger single-ended unipolar conversions on CH7 in
external clock mode without powering down between
conversions. In external clock mode, the SSTRB output
pulses high for two clock periods before the MSB of the
14-bit conversion result is shifted out of DOUT. Varying
the analog input to CH7 alters the sequence of bits
from DOUT. A total of 18 clock cycles are required per
conversion (Figure 10). All transitions of the SSTRB and
DOUT outputs occur on the falling edge of SCLK.
MAX1148
MAX1149
CH0
ANALOG INPUT MUX
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
IN+
IN-
TRACK
HOLD
CT/H+
CT/H-
TRACK
REF
14-BIT
CAPACITIVE
DAC
14-BIT
CAPACITIVE
DAC
REF
HOLD
Figure 6. Equivalent Input Circuit
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1149CGP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1149CUP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1149EGP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1149EUP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1149EUP-T | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Tape and Reel |
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