參數(shù)資料
型號: MAX1148BEUP+T
廠商: Maxim Integrated Products
文件頁數(shù): 21/25頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 116KSPS 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 14
采樣率(每秒): 116k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 879mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,單極;4 個差分,雙極
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
_______________________________________________________________________________________
5
Note 1: Tested at VDD = 3.0V (MAX1147/MAX1149) or 5.0V(MAX1146/MAX1148); VCOM = 0; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled. Measured with external reference.
Note 4: “On” channel grounded; full-scale 1kHz sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (See
Figures 8–11.)
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Digital inputs equal VDD or DGND.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured as (VFS x 3.6V) - (VFS x 2.7V) for the MAX1147/MAX1149 and (VFS x 5.25V) - (VFS x 4.75V) for the
MAX1146/MAX1148. VDD = 3.6V to 2.7V for MAX1147/MAX1149 and VDD = 5.25V to 4.75V for the MAX1146/MAX1148.
TIMING CHARACTERISTICS
(VDD = 4.75V to 5.25V (MAX1146/MAX1148), VDD = 2.7V to 3.6V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz,
external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2F, external +4.096V reference at REF
for the MAX1146/MAX1148, external 2.500V reference at REF for the MAX1147/MAX1149, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.) (Figures 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIN to SCLK Setup Time
tDS
50
ns
DIN to SCLK Hold Time
tDH
0ns
SCLK Fall to Output Data Valid
tDOV
CLOAD = 50pF
10
80
ns
CS Fall to DOUT Enable
tDOE
CLOAD = 50pF
120
ns
CS Rise to DOUT Disable
tDOD
CLOAD = 50pF
120
ns
SHDN Rise CS Fall to SCLK Rise
Time
tCSS
50
ns
SHDN Rise CS Fall to SCLK Rise
Hold Time
tCSH
50
ns
External clock mode
0.1
2.1
SCLK Clock Frequency
fSCLK
Internal clock mode
0
2.1
MHz
SCLK Pulse-Width High
tCH
Internal clock mode
100
ns
SCLK Pulse-Width Low
tCL
Internal clock mode
100
ns
CS Fall to SSTRB Output Enable
tSTE
External clock mode only
120
ns
CS Rise to SSTRB Output Disable
tSTD
External clock mode only
120
ns
SSTRB Rise to SCLK Rise
tSCK
Internal clock mode only
0
ns
SCLK Fall to SSTRB Edge
tSCST
80
ns
CS Pulse Width
tCSW
100
ns
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