參數(shù)資料
型號(hào): MAX1132BEAP+T
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 2/19頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT 200KSPS 20-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 16
采樣率(每秒): 200k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 55mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 1 個(gè)單端,單極;1 個(gè)單端,雙極
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
10
______________________________________________________________________________________
Table 1. Control Byte Format
BIT
NAME
DESCRIPTION
7 (MSB)
START
The first logic “1” bit, after
CS goes low, defines the beginning of the Control Byte
6
UNI/
BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog
input signals from 0 to +12V (MAX1132) or 0 to VREF (MAX1133) can be converted. In bipolar
mode analog input signals from -12V to +12V (MAX1132) or -VREF to +VREF (MAX1133) can be
converted.
5
INT/
EXT
Selects the internal or external conversion clock. 1 = Internal, 0 = External.
4M1
M1
M0
MODE
0
24 External clocks per conversion (short acquisition mode)
0
1
Start Calibration. Starts internal calibration.
1
0
Software power-down mode
3M0
1
32 External clocks per conversion (long acquisition mode)
2
1
0(LSB)
P2
P1
P0
These three bits are stored in a port register and output to pins P2, P1, P0 for use in addressing
a mux or PGA. These three bits are updated in the port register simultaneously when a new
Control Byte is written.
Table 2. User-Programmable Outputs
OUTPUT
PIN
PROGRAMMED
THROUGH
CONTROL BYTE
POWER-ON
OR
RST
DEFAULT
DESCRIPTION
P2
Bit 2
0
P1
Bit 1
0
P0
Bit 0
0
User-programmable outputs follow the state of the Control Byte’s three LSBs
and are updated simultaneously when a new Control Byte is written. Outputs
are push-pull. In hardware and software shutdown, these outputs are
unchanged and remain low-impedance.
ACQUISITION
CONVERSION
IDLE
SCLK
DOUT
A/D
STATE
DIN
SSTRB
CS
4
18
12
START
M1
M0
P2
P1
P0
UNI/
BIP
INT/
EXT
15
21
24
B12
B11
B14
B13
B10
B9
B4
B15
MSB
B0
LSB
FILLED WITH
ZEROS
B2
B3
B1
tACQ
Figure 2. Short Acquisition Mode (24-Clock Cycles) External Clock, Bipolar Mode
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