參數(shù)資料
型號: MAX1124EGK+D
廠商: Maxim Integrated Products
文件頁數(shù): 6/17頁
文件大小: 0K
描述: IC ADC 10BIT LVDS/PAR 68QFN-EP
標(biāo)準(zhǔn)包裝: 30
位數(shù): 10
采樣率(每秒): 250M
數(shù)據(jù)接口: LVDS,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 657mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)單端,單極;1 個(gè)差分,單極
MAX1124
determined resistor value between REFADJ and REFIO
increases the full-scale range of the data converter.
Figure 6 shows the two possible configurations and
their impact on the overall full-scale range adjustment
of the MAX1124. Do not use resistor values of less than
13kΩ to avoid instability of the internal gain regulation
loop for the bandgap reference.
Differential, AC-Coupled, PECL-Compatible
Clock Input
The preferred method of clocking the MAX1124 is differ-
entially with LVDS- or PECL-compatible input levels. To
accomplish this, a 50Ω reverse-terminated clock signal
source with low phase noise is AC-coupled into a fast
differential receiver such as the MC100LVEL16 (Figure
7). The receiver produces the necessary PECL output
levels to drive the clock inputs of the data converter.
Differential, AC-Coupled Analog Input
An RF transformer provides an excellent solution to
convert a single-ended source signal to a fully differen-
tial signal, required by the MAX1124 for optimum
dynamic performance. In general, the MAX1124 pro-
vides the best SFDR and THD with fully differential input
signals and it is not recommended to drive the ADC
inputs in single-ended configuration. In differential input
mode, even-order harmonics are usually lower since
INP and INN are balanced, and each of the ADC inputs
only requires half the signal swing compared to a sin-
gle-ended configuration.
Figure 8 depicts a secondary-side termination of the 1:1
transformer into two separate 25Ω loads. Terminating
the transformer in this fashion reduces the potential
effects of transformer parasitics. The source impedance
combined with the shunt capacitance provided by a
PCB and the ADC’s parasitic capacitance reduce the
combined bandwidth to approximately 550MHz.
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX1124 can be used
in single-ended mode (Figure 9). Analog signals can be
AC-coupled to the positive input INP through a 0.1F
capacitor and terminated with a 50Ω resistor to AGND.
The negative input should be 25Ω reverse-terminated
and AC grounded with a 0.1F capacitor.
Grounding, Bypassing, and Board
Layout Considerations
The MAX1124 requires board layout design techniques
suitable for high-speed data converters. This ADC pro-
vides separate analog and digital power supplies. The
analog and digital supply voltage pins accept input
voltage ranges of 1.7V to 1.9V. Although both supply
types can be combined and supplied from one source,
it is recommended to use separate sources to cut down
on performance degradation caused by digital switch-
ing currents, which can couple into the analog supply
network. Isolate analog and digital supplies (AVCC and
OVCC) where they enter the PCB with separate networks
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
14
______________________________________________________________________________________
MAX1124
10
D0P/N–D9P/N
AVCC
OVCC
AGND
OGND
INP
INN
25
Ω
25
Ω
15
Ω
15
Ω
ADT1–1WT
0.1
μF
0.1
μF
SINGLE-ENDED
INPUT TERMINAL
Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination
MAX1124
10
D0P/N–D9P/N
AVCC
OVCC
AGND
OGND
0.1
μF
SINGLE-ENDED
INPUT TERMINAL
0.1
μF
INP
INN
50
Ω
25
Ω
Figure 9. Single-Ended AC-Coupled Analog Input
Configuration
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