參數(shù)資料
型號: MAX11211EEE+
廠商: Maxim Integrated Products
文件頁數(shù): 14/27頁
文件大小: 0K
描述: ADC 18BIT DELTA-SIGMA 16-QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
位數(shù): 18
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 667mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-QSOP
包裝: 管件
輸入數(shù)目和類型: *
21
Maxim Integrated
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
MAX11209/MAX11211
DATA: Data Register
The data register is a 24-bit read-only register. Any attempt to write data to the data register has no effect. The data
read from this register is clocked out MSB first. The data register holds the conversion result. D17 is the MSB, and D0
is the LSB. The result is stored in a format according to the FORMAT bit in the CTRL1 register.
The data format while in unipolar mode is always straight binary. In straight binary format, the most negative value is
0x00000 (VAINP - VAINN = 0V), the midscale value is 0x20000 (VAINP - VAINN = VREF/2), and the most positive value
is 0x3FFFF (VAINP - VAINN = VREF).
In bipolar mode, if the FORMAT bit = 1, then the data format is offset binary. If the FORMAT bit = 0, then the data
format is two’s complement. In two’s complement the negative full-scale value is 0x20000 (VAINP - VAINN = -VREF), the
midscale is 0x00000 (VAINP - VAINN = 0V), and the positive full scale is 0x1FFFF (VAINP - VAINN = VREF). Any input
exceeding the available input range is limited to the minimum or maximum data value.
Table 15. DATA Register (Read Only)
Table 16a. Output Data Format for the Unipolar Input Range
BIT
D17
D16
D15
D14
D13
D12
D11
D10
DEFAULT
0
BIT
D9
D8
D7
D6
D5
D4
D3
D2
DEFAULT
0
BIT
D1
D0
0
DEFAULT
0
INPUT VOLTAGE
VAINP - VAINN
DIGITAL OUTPUT CODE FOR UNIPOLAR RANGE
STRAIGHT BINARY FORMAT
≥ VREF
0x3FFFF
0x00001
0
0x00000
REF
18
1
V1
21
×
REF
18
V
21
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