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| 型號(hào)： | MAX11201BEUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SRL 13.75SPS 10UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 13.75 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 444mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | * |
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______________________________________________________________________________________ 11
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Figure 1. Timing Diagram for Data Read After Conversion
Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK
Data Read Followed by Self-Calibration
To initiate self-calibration at the end of a data read, pro-
vide a 26th SCLK clock pulse. After reading the 24 bits
of conversion data, a 25th positive edge on SCLK pulls
the RDY/DOUT output back high, indicating the end of
the data read. Provide a 26th SCLK clock pulse to initi-
ate a self-calibration routine starting on the falling edge
of the SCLK. A subsequent falling edge of RDY/DOUT
indicates data availability at the end of calibration. The
timing is illustrated in Figure 3.
Data Read Followed by Sleep Mode
The MAX11201 can be put into sleep mode to save
power between conversions. To activate the sleep mode,
idle the SCLK high any time after the RDY/DOUT output
goes low (that is, after conversion data is available). It is
not required to read out all 24 bits before putting the part
in sleep mode. Sleep mode is activated after the SCLK is
held high (see Figure 4). The RDY/DOUT output is pulled
high once the device enters sleep mode. To come out
of the sleep mode, pull SCLK low. After the sleep mode
is deactivated (when the device wakes up), conversion
starts again and RDY/DOUT goes low, indicating the
next conversion data is available (see Figure 4).
Single-Conversion Mode
For operating the MAX11201 in single-conversion mode,
activate and deactivate sleep mode between conver-
sions as described in the Data Read Followed by Sleep
Mode section). Single-conversion mode reduces power
consumption by shutting down the device when idle
between conversions. See Figure 4.
t5
t3
1
D23
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE
D22
D0
2
3
24
t1
t4
t7
t2
t6
SCLK
RDY/DOUT
1
D23
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE
D22
D0
2
3
24
25
SCLK
RDY/DOUT
25TH SLK RISING EDGE
PULLS RDY/DOUT
HIGH
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX11201EUB+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24 Bit Sigma Delta ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11201EUB+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24 Bit Sigma Delta ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11202 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface |
| MAX11202_12 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface |
| MAX11202AEUB | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface |
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