參數(shù)資料
型號: MAX1115EKA+T
廠商: Maxim Integrated Products
文件頁數(shù): 12/12頁
文件大?。?/td> 0K
描述: IC ADC 8-BIT 100KSPS SOT23-8
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
位數(shù): 8
采樣率(每秒): 100k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 410µW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 1 個(gè)單端,單極
產(chǎn)品目錄頁面: 1395 (CN2011-ZH PDF)
其它名稱: MAX1115EKA+TDKR
After CNVST is brought low, allow 7.5s for the conver-
sion to be completed. While the internal conversion is in
progress, DOUT is low. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
and is coded in straight binary (Figure 7). Data is
clocked out at SCLK’s falling edge in MSB-first format
at rates up to 5MHz. Once all data bits are clocked out,
DOUT goes high impedance (100ns to 500ns after the
rising edge) of the eighth SCLK pulse.
SCLK is ignored during the conversion process. Only
after a conversion is complete will SCLK cause serial
data to be output. Falling edges on CNVST during an
MAX1115/MAX1116
Single-Supply, Low-Power, Serial 8-Bit ADCs
_______________________________________________________________________________________
9
ACTIVE
POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE LOW
CH0
tCSH
tCONV
tcp
tccs
tCSL
tchz
tcl
tcd
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
tcsd
tch
VDD
2
VDD
2
Figure 6c. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle Low
ACTIVE
POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE HIGH
CH0
tCSH
tCONV
tcp
tccs
tcsl
tchz
tcl
tcd
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
tcsd
tch
VDD
2
VDD
2
Figure 6d. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle High
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