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參數(shù)資料
| 型號： | MAX1115 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Single-Supply, Low-Power, Serial 8-Bit ADCs |
| 中文描述： | 單電源、低功耗、串行8位ADC |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 379K |
| 代理商： | MAX1115 |
M
Single-Supply, Low-Power, Serial 8-Bit ADCs
_______________________________________________________________________________________
3
Note 1:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and off-
set have been calibrated.
Note 2:
Input = 0, with logic input levels of 0 and V
DD
.
PARAMETER
SYMBOL
PSRR
CONDITIONS
MIN
TYP
±
0.5
MAX
±
1
UNITS
LSB/V
Supply Rejection Ratio
DIGITAL INPUTS (CNVST AND SCLK)
Input High Voltage
Input Low Voltage
Input Hystersis
Input Current High
Input Current Low
Input Capacitance
DIGITAL OUTPUT (DOUT)
Output High Voltage
Full-scale or zero input
V
IH
V
IL
V
HYST
I
IH
I
IL
C
IN
2
V
V
V
μA
μA
pF
0.8
0.2
±
10
±
10
2
V
OH
I
SOURCE
= 2mA
I
SINK
= 2mA
I
SINK
= 4mA
V
DD
- 0.5
V
0.4
0.8
±
10
Output Low Voltage
V
OL
V
Three-State Leakage Current
Three-State Output Capacitance
TIMING CHARACTERISTICS
(Figures 6a
–
6d)
CNVST High Time
CNVST Low Time
Conversion Time
Serial Clock High Time
Serial Clock Low Time
Serial Clock Period
I
L
±
0.01
4
μA
pF
C
OUT
t
csh
t
csl
t
conv
t
ch
t
cl
t
cp
100
100
ns
ns
μs
ns
ns
ns
7.5
75
75
200
Falling of CNVST to DOUT
Active
t
csd
C
LOAD
= 100pF, Figure 1
100
ns
Serial Clock Falling Edge to
DOUT
t
cd
C
LOAD
= 100pF
10
100
ns
Serial Clock Rising Edge
To DOUT High-Z
t
chz
C
LOAD
= 100pF, Figure 2
100
500
ns
Last S er al C ock to N ext C N V S T
( successi ve conver si ons on C H 0)
t
ccs
50
ns
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V (MAX1115), V
DD
= +4.5V to +5.5V (MAX1116), T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
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