參數(shù)資料
型號: MAX1114
廠商: Maxim Integrated Products, Inc.
英文描述: 8-Bit, 150Msps Flash ADC
中文描述: 8位,150Msps閃速ADC
文件頁數(shù): 7/12頁
文件大小: 114K
代理商: MAX1114
Reference Inputs V RBF, V RBS , V R1, V R2,
V R3, V RT F, V RT S (CERQUAD package only)
These are five external reference voltage taps from -2V
(VRBF) to AGND (VRTF) which can be used to control
integral linearity over temperature. The taps can be driv-
en by op amps (Figure 2). These voltage level inputs
can be bypassed to AGND for further noise suppres-
sion, if so desired. VRB and VRT have force and sense
pins for monitoring the top and bottom voltage refer-
ences.
Not Connec ted (N.C.)
All N.C. pins should be tied to DGND on the left side of
the package and to AGND on the right side of the
package.
Data Ready and Data-Ready Inverse
DREADY , DRINV (CERQUAD pac kage only)
The data-ready pin is a flag that goes high or low at the
output when data is valid or ready to be received. It is
essentially a delay line that accounts for the time nec-
essary for information to be clocked through the
MAX1114’s decoders and latches. This function is use-
ful for interfacing with high-speed memory. Using the
data-ready output to latch the output data ensures mini-
mum setup and hold times. DRINV is a data-ready
inverse control pin (Figure 3).
Overrange Input D8
(CERQUAD pac kage only)
When the MAX1114 is in an overrange condition, D8
goes high and all data outputs go high as well. This
makes it possible to include the MAX1114 in higher res-
olution systems.
Operation
The MAX1114 has 256 preamp/comparator pairs that
are each supplied with the voltage from VRTF to VRBF
divided equally by the resistive ladder as shown in the
Functional Diagram This voltage is applied to the posi-
tive input of each preamplifier/comparator pair. An ana-
log input voltage applied at VIN is connected to the
negative inputs of each preamplifier/comparator pair.
The comparator states are then clocked through each
comparator's individual clock buffer. When CLK is low,
the master, or input stage, of the comparators com-
pares the analog input voltage to the respective refer-
ence voltage. When CLK changes from low to high, the
comparators are latched to the state prior to the clock
transition and output logic codes in sequence from the
top comparators, closest to VRTF (0V), down to the
point where the magnitude of the input signal changes
sign (thermometer code). The output of each compara-
tor is then registered into four 64-to-6 bit decoders
when C LK is changed from high to low. At the
decoders' output is a set of four 7-bit latches that are
enabled (track) when CLK changes from high to low.
From here, the outputs of the latches are coded into 6
LSBs from 4 columns and 4 columns are coded into 2
MSBs. Next are the MINV and LINV controls for output
inversions that consist of a set of eight XOR gates.
Finally, 8 ECL output latches and buffers are used to
drive the external loads. The conversion takes one
clock cycle from the input to the data outputs.
_________________Evaluation Boards
The MAX1114/MAX1125 evaluation kit (EV kit) demon-
strates the full performance of the MAX1114. This
board includes a voltage reference circuit, clock driver
circuit, output data latches and an on-board recon-
struction of the digital data. A separate EV kit manual
describing the operation of this board is also available.
Contact the factory for price and delivery.
M
8-Bit, 150Msps Flash ADC
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