參數(shù)資料
型號(hào): MAX11131ATI+T
廠商: Maxim Integrated Products
文件頁數(shù): 7/37頁
文件大小: 0K
描述: IC ADC 12BIT SRL 3MSPS 28TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 3M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.76W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX11131ATI+TDKR
15
Maxim Integrated
MAX11129–MAX11132
3Msps, Low-Power, Serial 12-/10-Bit,
8-/16-Channel ADCs
Input Bandwidth
The ADC’s input-tracking circuitry features a 1.5MHz
small-signal full-linear bandwidth to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. Anti-alias filtering of the input
signals is necessary to avoid high-frequency signals
aliasing into the frequency band of interest.
3-Wire Serial Interface
The MAX11129–MAX11132 feature a serial interface
compatible with SPI/QSPI and MICROWIRE devices. For
SPI/QSPI, ensure the CPU serial interface runs in master
mode to generate the serial clock signal. Select the SCLK
frequency of 48MHz or less, and set clock polarity (CPOL)
and phase (CPHA) in the FP control registers to the same
value. The MAX11129–MAX11132 operate with SCLK
idling high, and thus operate with CPOL = CPHA = 1.
Set CS low to latch input data at DIN on the rising edge
of SCLK. Output data at DOUT is updated on the falling
edge of SCLK. A high-to-low transition on CS samples
the analog inputs and initiates a new frame. A frame is
defined as the time between two falling edges of CS.
There is a minimum of 16 bits per frame. The serial data
input, DIN, carries data into the control registers clocked
in by the rising edge of SCLK. The serial data output,
DOUT, delivers the conversion results and is clocked out
by the falling edge of SCLK. DOUT is a 16-bit data word
containing a 4-bit channel address, followed by a 12-bit
conversion result led by the MSB when CHAN_ID is set
to 1 in the ADC Mode Control register (Figure 2a). In
this mode, keep the clock high for at least one full SCLK
period before the CS falling edge to ensure best perfor-
mance (Figure 2b). When CHAN_ID is set to 0 (external
clock mode only), the 16-bit data word includes a lead-
ing zero and the 12-bit conversion result is followed by
3 trailing zeros (Figure 2c). In the 10-bit ADC, the last 2
LSBs are set to 0.
Figure 2a. External Clock Mode Timing Diagram with CHAN_ID=1
Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance
23
45
67
8
110111213141516
9
CS
SCLK
DIN
DOUT
MSB MSB-1
LSB
LSB+1
Ch[2] Ch[1] Ch[0]
DI[15]
DI[1]
Ch[3]
DI[0]
DI[14]
23
45
67
8
110111213141516
9
CS
SCLK
DIN
DOUT
MSB MSB-1
LSB
LSB+1
Ch[2] Ch[1] Ch[0]
DI[15]
DI[1]
Ch[3]
DI[0]
tQUIET > tSCLK
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MAX11131AUI+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 16 Ch 3Msps Serial ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX11131AUI+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 16 Ch 3Msps Serial ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX11131EVKIT# 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX11131 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
MAX11132 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3Msps, Low-Power, Serial 12-/10-Bit, 8-/16-Channel ADCs
MAX11132ATI+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 8Ch 3Msps Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32