參數(shù)資料
型號(hào): MAX1108CUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 6/20頁
文件大?。?/td> 0K
描述: IC ADC 8BIT LP 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 8
采樣率(每秒): 50k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 444mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極;1 個(gè)偽差分,單極;1 個(gè)偽差分,雙極
MAX1108/MAX1109
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
14
______________________________________________________________________________________
initiated. The MSB successive-approximation bit deci-
sion is made on the rising edge of the seventh SCLK.
On the falling edge of the eighth SCLK, the MSB is
clocked out on the DOUT pin; on each of the next
seven SCLK falling edges, the remaining bits of conver-
sion are clocked out. Zeros are clocked out on DOUT
after the LSB has been clocked out, until CS is dis-
abled. Then DOUT becomes high impedance and the
part is ready for another conversion (Figure 6).
The conversion must complete in 1ms, or droop on the
sample-and-hold capacitors may degrade conversion
results. Use internal clock mode if the serial-clock fre-
quency is less than 50kHz, or if serial-clock interruptions
could cause the conversion interval to exceed 1ms.
Internal Clock
Internal clock mode frees the P from the burden of
running the SAR conversion clock. This allows the con-
version results to be read back at the processor’s con-
venience, at any clock rate up to 2MHz.
An internal register stores data when the conversion is
in progress. On the falling edge of the fourth SCLK,
track mode is enabled, and on the falling edge of the
eighth SCLK, acquisition is complete and internal con-
version is initiated. The internal 400kHz clock com-
pletes the conversion in 20s typically (35s max), at
which time the MSB of the conversion is present at the
DOUT pin. The falling edge of SCLK clocks the remain-
ing data out of this register at any time after the conver-
sion is complete (Figure 8).
CS
SCLK
DIN
DOUT
14
8
12
16
20
START
SEL2
MSB
LSB
SEL1
SEL0
I/ECLK I/EREF
REF
SHDN
D7
MSB
LSB
D6
D5
D4
D3
D2
D1
D0
IDLE
tCONV
tACQ
A/D STATE
Figure 6. Single Conversion Timing, External Clock Mode
CS
SCLK
DIN
DOUT
tCSH
tCSS
tCL
tDS
tDH
tDV
tCH
tDO
tTR
tCSH
Figure 7. Detailed Serial-Interface Timing
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