參數(shù)資料
型號: MAX1107EUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/16頁
文件大?。?/td> 0K
描述: IC ADC 8BIT LP 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 8
采樣率(每秒): 25k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 580µW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;1 個偽差分,單極
Starting SCLK before conversion is complete corrupts
the conversion in progress, and the data clocked out at
DOUT does not represent the input signal. Bringing
CONVST high at anytime during a conversion or while
the data is clocked out will result in an incorrect conver-
sion. A new conversion can be restarted only if all eight
data bits of conversion have been clocked out. Toggle
CONVST after all data is clocked out to restart a new
conversion.
SHDN is used to place the MAX1106/MAX1107 in low-
power mode (see
Power-Down section). In this mode
DOUT is high impedance and any conversion in
progress is stopped immediately. If a conversion is
stopped by SHDN going low, the device must be reset
by waiting 35s and clearing the output register with
eight SCLKs before the next conversion.
How to Perform a Conversion
The MAX1106/MAX1107 converts an input signal using
the internal clock. This frees the P from the burden of
running the SAR conversion clock, and allows the con-
version results to be read back at the P’s convenience
at any clock rate up to 2MHz.
Figures 6 and 7 show the serial interface timing charac-
teristics. CONVST idles low. Toggle CONVST high for at
least 1s to perform the autozero adjustment. After
CONVST goes low, conversion starts immediately.
Allow 35s for the internal conversion to complete and
issue the MSB of the conversion at DOUT. CONVST
needs to be held low once a conversion is started,
while SCLK should remain low during conversion for
best noise performance. An internal register stores data
when the conversion is in progress. SCLK clocks the
CONVST
SCLK
1
s
(MIN)
HIGH-Z
DOUT
18
100
s (MAX)
D7
MSB
LSB
D6
D5
D4
D3
D2
D1
D0
tCONV = 35s (MAX)
CONVERSION
ACQUISITION
tCSPW
A/D STATE
ACQ
Figure 6. Conversion Timing Diagram
MAX1106/MAX1107
Single-Supply, Low-Power,
Serial 8-Bit ADCs
12
______________________________________________________________________________________
CONVST
SCLK
DOUT
I/O
SCK
MISO
+3V
SS
a) SPI
CONVST
SCLK
DOUT
CS
SCK
MISO
+3V
SS
b) QSPI
MAX1106
MAX1107
MAX1106
MAX1107
MAX1106
MAX1107
SCLK
DOUT
I/O
SK
SI
c) MICROWIRE
Figure 5. Common Serial-Interface Connections
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