參數(shù)資料
型號: MAX1107
廠商: Maxim Integrated Products, Inc.
英文描述: Single-Supply, Low-Power, Serial 8-Bit ADCs
中文描述: 單電源、低功耗、串行8位ADC
文件頁數(shù): 13/16頁
文件大?。?/td> 205K
代理商: MAX1107
M
S ingle-S upply, Low-Power,
S erial 8-Bit ADCs
______________________________________________________________________________________
13
data out of this register at any time after the conversion
is complete. After the eighth data-bit has clocked out,
DOUT goes high impedance and remains so with addi-
tional SCLKs.
Normally leave CONVST low until a new conversion
needs to be started. CONVST should be high for a
maximum of 100μs to maintain the 8-bit accuracy of the
Autozero Circuit.
The acquisition time, t
ACQ
, starts immediately after the
end of conversion and a new conversion can be started
immediately after all data has been clocked out by tog-
gling CONVST high. Figure 8 shows a timing diagram
for a conversion at the data rate of 40ksps. Typically
20μs are necessary for the conversion to complete, 4μs
for reading the eight bits of data with a serial clock of
2MHz, and 1μs to complete the zero rail adjustment
and acquisition. The conversion time is guaranteed to
be less than 35μs, therefore the data rate should be
limited to 25ksps unless the conversion time for the
specific condition is known. Conversion time can be
determined by measuring the time between CONVST
falling edge and DOUT rising edge with a full-scale
input voltage.
__________Applic ations Information
Power-On Reset
When power is first applied with
SHDN
high or connect-
ed to V
DD
, the MAX1106/MAX1107 is in track mode.
Conversion can be started by toggling CONVST high to
low as soon as the reference is settled when using the
internal reference, or after 20μs when an external refer-
ence is used. Powering up the MAX1106/MAX1107 with
CONVST low will not start a conversion. No conversions
should be performed until the reference voltage (inter-
nal or external) has stabilized.
S hutdown Operation
Pulling
SHDN
low places the converter in low-current
power-down mode. In this state the converter draws
typically 0.5μA. In shutdown the analog biasing circuit
and the internal bandgap reference are powered down,
and DOUT goes high impedance.
The conversion stops coincidentally with
SHDN
going
low. If shutdown occurs during a conversion, power up,
wait 35μs, and clock SCLK eight times.
CONVST
SCLK
DOUT
t
CSPW
t
CONV
t
DV
t
CH
#1
#8
t
CL
t
DO
t
DV
t
TR
t
SCC
Figure 7. Detailed Serial Interface Timing
CONVST
5V/div
SCLK
5V/div
DOUT
5V/div
5
μ
s/div
t
CONV
Figure 8. 40ksps Timing Diagram
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