參數(shù)資料
型號(hào)： MAX11059ECB+T
廠商： Maxim Integrated Products
文件頁數(shù)： 5/25頁
文件大?。?/td> 0K
描述： IC ADC 14BIT PAR 250KSPS 64TQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 14
采樣率（每秒）： 250k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 3.48W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-TQFP-EP（10x10）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極
MAX11047–MAX11049/MAX11057–MAX11059
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
______________________________________________________________________________________
13
Pin Description (continued)
PIN
MAX11057
(TQFP-EP)
MAX11058
(TQFP-EP)
MAX11059
(TQFP-EP)
NAME
FUNCTION
1
DB12
14-Bit Parallel Data Bus Digital Output Bit 12
2
DB11
14-Bit Parallel Data Bus Digital Output Bit 11
3
DB10
14-Bit Parallel Data Bus Digital Output Bit 10
4
DB9
14-Bit Parallel Data Bus Digital Output Bit 9
5
DB8
14-Bit Parallel Data Bus Digital Output Bit 8
6
DB7
14-Bit Parallel Data Bus Digital Output Bit 7
7
DB6
14-Bit Parallel Data Bus Digital Output Bit 6
8, 22, 59
DGND
Digital Ground
9, 21, 60
DVDD
Digital Supply. Bypass to DGND with a 0.1F capacitor at each DVDD input.
10
DB5
14-Bit Parallel Data Bus Digital Output Bit 5
11
DB4
14-Bit Parallel Data Bus Digital Output Bit 4
12
DB3
14-Bit Parallel Data Bus Digital Output Bit 3
13
DB2
14-Bit Parallel Data Bus Digital Output Bit 2
14
DB1/CR3
14-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 3
15
DB0/CR2
14-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 2
16
CR1
Configuration Register Input Bit 1
17
CR0
Configuration Register Input Bit 0
18
EOC
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is
completed. EOC goes high when a conversion is initiated.
19
CONVST
Convert Start Input. The rising edge of CONVST ends sample and starts a
conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
20
SHDN
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
23, 28, 32,
38, 43, 49,
53, 58
23, 28, 32,
38, 43, 49,
53, 58
23, 28, 32,
38, 43, 49,
53, 58
AGNDS
Signal Ground. Connect all AGND and AGNDS inputs together.
24, 29, 35,
46, 52, 57
24, 29, 35,
46, 52, 57
24, 29, 35,
46, 52, 57
AVDD
Analog Supply Input. Bypass AVDD to AGND with a 0.1F capacitor at each
AVDD input.
25, 30, 36,
45, 51, 56
25, 30, 36,
45, 51, 56
25, 30, 36,
45, 51, 56
AGND
Analog Ground. Connect all AGND inputs together.
26, 55
RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane.
27, 33,
40,48, 54
27, 33,
40,48, 54
27, 33,
40,48, 54
RDC
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
AGND with at least an 80F total capacitance. See the Layout, Grounding,
and Bypassing section.
31, 34,
47, 50
31, 50
—
I.C.
Internally Connected. Connect to AGND.
37
34
31
CH0
Channel 0 Analog Input
39
37
34
CH1
Channel 1 Analog Input
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