參數(shù)資料
型號: MAX11049ETN+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/25頁
文件大小: 0K
描述: IC ADC 16BIT 250KSPS SAR 56TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
采樣率(每秒): 250k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 3.81W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-TQFN-EP(8x8)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極
MAX11047–MAX11049/MAX11057–MAX11059
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
12
______________________________________________________________________________________
Pin Description (continued)
PIN
MAX11047
(TQFP-EP)
MAX11048
(TQFP-EP)
MAX11049
(TQFP-EP)
NAME
FUNCTION
18
EOC
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is
completed. EOC goes high when a conversion is initiated.
19
CONVST
Convert Start Input. The rising edge of CONVST ends sample and starts a
conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
20
SHDN
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
23, 28, 32,
38, 43, 49,
53, 58
23, 28, 32,
38, 43, 49,
53, 58
23, 28, 32,
38, 43, 49,
53, 58
AGNDS
Signal Ground. Connect all AGND and AGNDS inputs together.
24, 29, 35,
46, 52, 57
24, 29, 35,
46, 52, 57
24, 29, 35,
46, 52, 57
AVDD
Analog Supply Input. Bypass AVDD to AGND with a 0.1F capacitor at each
AVDD input.
25, 30, 36,
45, 51, 56
25, 30, 36,
45, 51, 56
25, 30, 36,
45, 51, 56
AGND
Analog Ground. Connect all AGND inputs together.
26, 55
RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane.
27, 33, 40,
48, 54
27, 33, 40,
48, 54
27, 33, 40,
48, 54
RDC
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
AGND with at least an 80F total capacitance. See the Layout, Grounding,
and Bypassing section.
31, 34,
47, 50
31, 50
I.C.
Internally Connected. Connect to AGND.
37
34
31
CH0
Channel 0 Analog Input
39
37
34
CH1
Channel 1 Analog Input
41
REFIO
External Reference Input/Internal Reference Output. Place a 0.1F capacitor
from REFIO to AGND.
42
39
37
CH2
Channel 2 Analog Input
44
42
39
CH3
Channel 3 Analog Input
44
42
CH4
Channel 4 Analog Input
47
44
CH5
Channel 5 Analog Input
47
CH6
Channel 6 Analog Input
50
CH7
Channel 7 Analog Input
61
WR
Active-Low Write Input. Drive WR low to write to the ADC. Configuration
registers are loaded on the rising edge of WR.
62
CS
Active-Low Chip-Select Input. Drive CS low when reading from or writing to
the ADC.
63
RD
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge
of RD advances the channel output on the data bus.
64
DB15
16-Bit Parallel Data Bus Digital Out Bit 15
——
EP
Exposed Pad. Internally connected to AGND. Connect to a large ground
plane to maximize thermal performance. Not intended as an electrical
connection point.
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MAX1104EUA+TW 功能描述:ADC / DAC多通道 8-Bit CODEC +2.7V to +5.5V Single Supply RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1104EUA+W 功能描述:ADC / DAC多通道 8-Bit CODEC +2.7V to +5.5V Single Supply RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40