
M
Detailed Description
The MAX11041/MAX11042 wired remote controllers
recognize either six or 30 different keypresses consist-
ing of a resistor/switch array over a single connector.
Designed for wired remote controllers on the head-
phone or headset cord, the MAX11041/MAX11042
contain debouncing circuitry and jack insertion/
removal detection. During a keypress, the MAX11041/
MAX11042 store the key type and key duration in an 8-
word FIFO and
INT
(interrupt output) goes low. The
results stored in the FIFO are accessed through the I
2
C
interface.
FORCE and SENSE
During a keypress, a unique external resistor (R
SW_
)
located in the remote controller connects SENSE to
ground (Figure 2). This event changes the impedance
seen by the SENSE line. The MAX11041/MAX11042
decode this resistor value to an 8-bit result (see the
Required Resistor Set
section). FORCE and SENSE are
±15kV ESD (IEC 61000-4-2) protected.
Register Description
The MAX11041/MAX11042 contain one 8-bit control
register, an 8-word FIFO (each word consists of an 8-
bit key value and an 8-bit duration value), and an 8-bit
chip ID.
Chip ID
The chip ID identifies the features and capabilities of the
wired remote controller to the software. For the
MAX11041, the chip ID is 0x00. For the MAX11042, the
chip ID is 0x01.
Control Register
The MAX11041/MAX11042 contain one control register
(see Table 1). Bits C7, C6, and C5 control software shut-
down. Set FORCE high-impedance and indicate if the
FIFO is empty. Write/read to the control register through
the I
2
C-compatible serial interface (see the
Digital Serial
Interface
section).
FIFO
The MAX11041/MAX11042 contain an 8-word FIFO that
can hold enough information for four keypresses and
releases. Each keypress and release results in two data
words being stored into the FIFO. Each FIFO word con-
sists of 2 bytes. The 1st byte is the decoded keypress or
release (K7–K0) and the 2nd byte is the keypress or
release duration time. Table 2 shows the format of a key-
press entry into the FIFO. Read the FIFO through the I
2
C-
compatible serial interface (see the
Digital Serial
Interface
section). At power-up, all the FIFO is reset such
that K7–K0 are set to 0xFF hex and 0x0F, and T6–T0 are
set to 0x00. See the
Applications Information
section for
an example of how data is entered into the FIFO.
Wired Remote Controllers
6
_______________________________________________________________________________________
Pin Description
PIN
TQFN
1
UCSP
D1
NAME
FUNCTION
GND
Ground
Voltage Sense Input. Connect SENSE to FORCE through an external lowpass filter
composed of R
SENSE
and C
SENSE
(see the
FORCE and SENSE
section). There is a ±15kV
IEC61000-4-2 ESD protection on SENSE.
Power-Supply Input. Connect both V
DD
inputs together and bypass each V
DD
with a 0.1μF
capacitor to GND.
No Connection. Leave unconnected or connect to V
DD
.
I
2
C Address Input 1. Logic state represents bit 1 of the I
2
C slave address.
I
2
C Address Input 0. Logic state represents bit 0 of the I
2
C slave address.
2
C1
SENSE
3, 11
B1, D3
V
DD
4
5
6
A1
A2
A3
N.C.
A1
A0
7
A4
SHDN
Active-Low Shutdown Input. Bring
SHDN
low to put the MAX11041/MAX11042 in shutdown
mode. FORCE is in a high-impedance state while
SHDN
is low.
I
2
C Serial-Interface Clock Input. SCL requires a pullup resistor.
I
2
C Serial-Interface Data Input/Output. SDA requires a pullup resistor.
Active-Low Interrupt Output.
INT
goes low when a valid keypress is detected at SENSE.
8
9
10
B4
C4
D4
SCL
SDA
INT
12
D2
FORCE
Force Output. Connect FORCE to the external resistor array. Connect SENSE to FORCE
through an external lowpass filter composed of R
SENSE
= 10k
and C
SENSE
= 10nF. There
is a ±15kV IEC61000-4-2 ESD protection on FORCE.
EP
—
EP
Exposed Pad. Connect EP to GND.