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參數(shù)資料
| 型號： | MAX11040GUU+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/35頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 4CH 38-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 64k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 108mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 38-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
| 配用： | MAXSPCSPARTAN6+-ND - ADC and DAC Eval Expansion Board |
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MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
17
Maxim Integrated
DRDYIN, and DRDYOUT. For single-device applications,
connect CASCIN and DRDYIN to DGND and drive CS
low to transfer data in and out of the devices. With
DRDYIN low, a falling edge at the data-ready signal out-
put (DRDYOUT) indicates that new conversion results
are available for reading in the 96-bit data register. A
falling edge on SCLK clocks in data at DIN. Data at
DOUT changes on the rising edge of SCLK and is valid
on the falling edge of SCLK. DIN and DOUT are trans-
ferred MSB first. Drive CS high to disable the interface
and place DOUT in a high-impedance state.
An interface operation with the devices takes effect on
the last rising edge of SCLK. If CS goes high before the
complete transfer, the write is ignored. Every data
transfer is initiated by the command byte. The com-
mand byte consists of an R/W bit and 7 address bits
(see Table 2.) Figures 7 and 8 show the timing for read
and write operations, respectively.
tCSW
SCLK
CS
DIN
DOUT
DRDYIN
HIGH-Z
B7 B6 B5 B4 B3 B2 B1 B0
tSU
tSCP
tDCD
tCSH1
tSU
tDOE
tDRDY
DATA READY
tHD
COMMAND ADDRESS
tDOT
tPW
R/W A6 A5
A3 A2 A1 A0
A4
DATA LENGTH (NUMBER OF BYTES) DEPENDS
ON THE REGISTER BEING READ (SEE TABLE 2)
DRDYOUT
Figure 7. General Read-Operation Timing Diagram
DOUT
HIGH-Z
tCSW
tSU
tHD
tSU
tPW
tSCP
tPW
tCSH1
CS
DIN
SCLK
A6 A5
A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1
R/W
B0
DATA LENGTH (NUMBER OF BYTES) DEPENDS ON
THE REGISTER BEING WRITTEN (SEE TABLE 2)
A4
Figure 8. General Write-Operation Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX11040K | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs |
| MAX11040K_1111 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs |
| MAX11040K_12 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:MAX11040K Evaluation Kit/Daughterboard |
| MAX11040KDBEVKIT | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:MAX11040K Evaluation Kit/Daughterboard |
| MAX11040KDBEVKIT# | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX5135/11040/11612 Eval Kit w/ FMC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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