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參數(shù)資料
| 型號(hào)： | MAX1101 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA |
| 中文描述： | 單芯片，8位數(shù)字化儀與防治荒漠化公約鉗位和6位美國(guó)PGA |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | MAX1101 |
M
S ingle-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
4
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
NAME
FUNCTION
1, 3, 5, 7,
10, 16, 24
2
4
6
8, 9, 10
GND
Ground
CCDIN
AIN1
AIN2
I.C.
CCD Input. Connect CCD through a series 0.047μF capacitor (C
EXT
).
Auxiliary Analog Input Channel 1
Auxiliary Analog Input Channel 2
Internally Connected. Do not connect to this pin.
PIN
12
REF-
Lower Limit of Reference Span. Sets the zero-code voltage. Range is GND
≤
REF-
≤
REF+.
Nominally 0.5V.
11
REFGND
Reference Ground. Ground reference for all analog signals.
18
19
20
21
22
SCLK
DATA
LOAD
VIDSAMP
CLAMP
Serial Clock Input
Data Input or Output, as controlled by MODE
Control Input. Loads serial shift-register data to PGA and multiplexer registers when MODE = 0.
Control Input. Samples the video level and initiates the ADC conversion.
Control Input. Samples black level. Can be used for correlated double sampling.
17
MODE
Control Input. Set high, DATA is an output of the ADC. Set low, DATA enables programming of the
PGA and mux.
15, 23
V
DD
Power Supply, +5V. Bypass to ground very close to the device and connect the two pins together,
close to the MAX1101.
14
REFBIAS
Reference Power Supply. Connect to external +5.0V to set V
REF+
to +3.0V and V
REF-
to +0.5V.
13
REF+
Upper Limit of Reference Span. Sets the full-scale input. Voltage range is REF-
≤
REF+
≤
V
DD
.
Nominally 3.0V.
_______________Detailed Desc ription
Overview
The MAX1101 directly processes the pixel stream from
a monochrome CCD, and removes black level, offset,
and noise errors through an internal clamp circuit,
which can be used as a correlated double sampler
(CDS). It uses a 6-bit, programmable-gain amplifier
(PGA) to adjust gain. A three-input multiplexer (mux)
selects either the PGA output or two unassigned inputs
(AIN1, AIN2). The processed analog signal is digitized
by an 8-bit, half-flash analog-to-digital converter (ADC),
and output serially through the DATA pin.
Digital data is input and output through the bidirectional
serial pin (DATA) synchronously with the external serial
clock (SCLK). When MODE = 0, the mux channels and
the PGA gain can be programmed via DATA. With MODE
= 1 (high), ADC serial data is output through this pin.
PGA
GAIN
CLAMP
CIRCUIT
MUX
ADC
REGISTER
REGISTER
6
2
6
2
1
0
2
8
8
SERIAL
PORT
DATA
SCLK
LOAD
MODE
REFBIAS
REF+
REF-
REFGND
AIN2
AIN1
CLAMP
CCDIN
VIDSAMP
REGISTER
Figure 1. MAX1101 Functional Diagram
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