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參數資料
| 型號： | MAX1085BESA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 400ksps/300ksps, Single-Supply, Low-Power, Serial 10-Bit ADCs with Internal Reference |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數： | 5/16頁 |
| 文件大?。?/td> | 235K |
| 代理商： | MAX1085BESA |
M
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS—MAX1084
(Figures 1, 2, 8, 9; V
DD
= +4.5V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
SYMBOL
PARAMETER
TIMING CHARACTERISTICS—MAX1085
(Figures 1, 2, 8, 9; V
DD
= +2.7V to +3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
CONDITIONS
ns
100
t
CSW
CS
Pulse Width High
ns
ns
ns
ns
ns
62
35
0
35
35
t
CL
t
CSS
t
CSH
t
CSO
t
CS1
SCLK Pulse Width Low
CS
Fall to SCLK Rise Setup
SCLK Rise to
CS
Rise Hold
SCLK Rise to
CS
Fall Ignore
CS
Rise to SCLK Rise Ignore
ns
62
t
CH
ns
156
t
CP
SCLK Period
SCLK Pulse Width High
ns
65
t
DOE
CS
Fall to DOUT Enable
ns
10
65
t
DOD
CS
Rise to DOUT Disable
ns
80
t
DOV
SCLK Rise to DOUT Valid
ns
10
t
DOH
SCLK Rise to DOUT Hold
UNITS
MIN
TYP
MAX
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
CONDITIONS
ns
ns
ns
ns
ns
83
45
0
45
45
t
CL
t
CSS
t
CSH
t
CSO
t
CS1
SCLK Pulse Width Low
CS
Fall to SCLK Rise Setup
SCLK Rise to
CS
Rise Hold
SCLK Rise to
CS
Fall Ignore
CS
Rise to SCLK Rise Ignore
ns
83
t
CH
ns
208
t
CP
SCLK Period
SCLK Pulse Width High
ns
ns
ns
13
85
85
t
DOD
t
DOE
t
CSW
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
CS
Pulse Width High
ns
100
t
DOV
SCLK Rise to DOUT Valid
ns
13
t
DOH
SCLK Rise to DOUT Hold
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Note 1:
Tested at V
DD
= V
DD,MIN
.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
Internal reference, offset, and reference errors nulled.
Note 4:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:
External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitation.
Note 6:
Electrical characteristics are guaranteed from V
DD,MIN
to V
DD,MAX
. For operations beyond this range, see
Typical Operating
Characteristics.
Note 7:
MAX1084 tested with 20pF on DOUT and f
SCLK
= 6.4MHz, 0 to 5V. MAX1085 tested with same loads, f
SCLK
= 4.8MHz, 0 to
3V. DOUT = full scale.
100
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