參數(shù)資料
型號: MAX1085BCSA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 400ksps/300ksps, Single-Supply, Low-Power, Serial 10-Bit ADCs with Internal Reference
中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 8/16頁
文件大小: 235K
代理商: MAX1085BCSA
M
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
8
_______________________________________________________________________________________
_______________Detailed Description
Converter Operation
The MAX1084/MAX1085 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 10-bit output.
Figure 3 shows the MAX1084/MAX1085 in their simplest
configuration. The internal reference is trimmed to 2.5V.
The serial interface requires only three digital lines
(SCLK,
CS
,
and DOUT) and provides an easy interface to
microprocessors (
μ
Ps).
The MAX1084/MAX1085 have two modes: normal and
shutdown. Pulling
SHDN
low shuts the device down and
reduces supply current to 2μA (typ); pulling
SHDN
high
puts the device into operational mode. Pulling
CS
low ini-
tiates a conversion that is driven by SCLK. The conver-
sion result is available at DOUT in unipolar serial format.
The serial data stream consists of three zeros, followed
by the data bits (MSB first). All transitions on DOUT
occur 20ns after the rising edge of SCLK. Figures 8 and
9 show the interface timing information.
Analog Input
Figure 4 shows the sampling architecture of the ADC’s
comparator. The full-scale input voltage is set by the
internal reference (V
REF
= +2.5V).
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor C
HOLD
. Bringing
CS
low ends the acquisition
interval. At this instant, the T/H switches the input side
of C
HOLD
to GND. The retained charge on C
HOLD
repre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 10-
bit resolution. This action is equivalent to transferring a
charge from C
HOLD
to the binary-weighted capacitive
DOUT
DOUT
6k
DGND
C
LOAD
= 20pF
C
LOAD
= 20pF
6k
DGND
V
DD
b)
HIGH-Z TO V
OL
AND V
OH
TO V
OL
a)
HIGH-Z TO V
OH
AND V
OL
TO V
OH
DOUT
DOUT
6k
DGND
C
LOAD
= 20pF
C
LOAD
= 20pF
6k
DGND
V
DD
b)
V
OL
TO HIGH-Z
a)
V
OH
TO HIGH-Z
Figure 1. Load Circuits for DOUT Enable Time
Figure 2. Load Circuits for DOUT Disable Time
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