參數(shù)資料
型號(hào): MAX107EVKIT
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 7/21頁(yè)
文件大?。?/td> 0K
描述: EVAL KIT FOR MAX107
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 2
位數(shù): 6
采樣率(每秒): 400M
數(shù)據(jù)接口: 并聯(lián)
輸入范圍: 800 mVpp
在以下條件下的電源(標(biāo)準(zhǔn)): 2.6W @ 400MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: MAX105,MAX107
已供物品:
edge of the data ready clock. The auxiliary data port
always contains the older sample. The primary output
always contains the most recent data sample, regard-
less of the DREADY clock phase. Figure 7 shows the
timing and data alignment of the auxiliary and primary
output ports in relationship with the CLK and DREADY
signals. Data in the primary port is delayed by five
clock cycles while data in the auxiliary port is delayed
by six clock cycles.
Typical I/Q Application
Quadrature amplitude modulation (QAM) is frequently
used in digital communication systems to increase
channel capacity. A QAM signal is modulated in both
amplitude and phase. With a demodulator, this QAM
signal gets downconverted and separated in its in-
phase (I) and quadrature (Q) components. Both I&Q
channels are digitized by an ADC at the baseband
level in order to recover the transmitted information.
Figure 8 shows a typical application circuit to directly
tune L-band signals to baseband, incorporating a
direct conversion tuner (MAX2108) and the MAX107 to
digitize I&Q channels with excellent phase- and gain-
matching. A front-end L-C filter is required for anti-alias-
ing purposes.
MAX107
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
______________________________________________________________________________________
15
Figure 7. Output Timing Relationship Between CLK and DREADY Signals and Primary/Auxiliary Output Ports
CLK+
CLK-
DREADY +
DREADY -
AUXILIARY PORT DATA
PRIMARY PORT DATA
tPWH
tPWL
tPD1
tPD2
NOTE: THE LATENCY TO THE PRIMARY PORT IS FIVE CLOCK CYCLES, THE LATENCY TO THE AUXILIARY PORT IS SIX CLOCK
CYCLES. BOTH PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
CLK-
CLK+
N
N+1
N+2
N+3
N+4
N+5
N
N+8
N+10
N+2
N+6
N+4
N+6
N+7
N+8
N+9
N+10
N+11
N+12
N+13
ADC SAMPLE
MAX107 ADCs SAMPLE ON THE RISING EDGE OF CLK+
CLK
DREADY
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
DREADY-
DREADY+
N+14
N+15
N+16
N+17
N+18
N+19
N+9
N+11
N+3
N+1
N+7
N+5
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參數(shù)描述
MAX108 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:【5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
MAX1080 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference
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