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參數(shù)資料
| 型號： | MAX107ECS |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier |
| 中文描述： | 2-CH 6-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP80 |
| 封裝： | 12 X 12 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-80 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 1423K |
| 代理商： | MAX107ECS |
edge of the data ready clock. The auxiliary data port
always contains the older sample. The primary output
always contains the most recent data sample, regard-
less of the DREADY clock phase.
Figure 7 shows the
timing and data alignment of the auxiliary and primary
output ports in relationship with the CLK and DREADY
signals. Data in the primary port is delayed by five
clock cycles while data in the auxiliary port is delayed
by six clock cycles.
Typical I/Q Application
Quadrature amplitude modulation (QAM) is frequently
used in digital communication systems to increase
channel capacity. A QAM signal is modulated in both
amplitude and phase. With a demodulator, this QAM
signal gets downconverted and separated in its in-
phase (I) and quadrature (Q) components. Both I&Q
channels are digitized by an ADC at the baseband
level in order to recover the transmitted information.
Figure 8 shows a typical application circuit to directly
tune L-band signals to baseband, incorporating a
direct conversion tuner (MAX2108) and the MAX107 to
digitize I&Q channels with excellent phase- and gain-
matching. A front-end L-C filter is required for anti-alias-
ing purposes.
M
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
______________________________________________________________________________________
15
Figure 7. Output Timing Relationship Between CLK and DREADY Signals and Primary/Auxiliary Output Ports
CLK+
CLK-
DREADY +
DREADY -
AUXILIARY PORT DATA
PRIMARY PORT DATA
t
PWH
t
PWL
t
PD1
t
PD2
NOTE:
THE LATENCY TO THE PRIMARY PORT IS FIVE CLOCK CYCLES, THE LATENCY TO THE AUXILIARY PORT IS SIX CLOCK
CYCLES. BOTH PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
CLK-
CLK
CLK+
N
N+1
N+2
N+3
N+4
N+5
N
N+8
N+10
N+2
N+6
N+4
N+6
N+7
N+8
N+9
N+10
N+11
N+12
N+13
ADC SAMPLE
MAX107 ADCs SAMPLE ON THE RISING EDGE OF CLK+
DREADY
DREADY+
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
DREADY-
N+14
N+15
N+16
N+17
N+18
N+19
N+9
N+11
N+3
N+1
N+7
N+5
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相關(guān)代理商/技術(shù)參數(shù) |
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| MAX107ECS+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 6-Bit 400Msps w/OnChip Wdbnd InAmp RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX107ECS+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 6-Bit 400Msps w/OnChip Wdbnd InAmp RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX107ECS-D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX107ECS-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX107EVKIT | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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