參數(shù)資料
型號(hào): MAX1071ETC+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 5/18頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 1.5MSPS 12-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
采樣率(每秒): 1.5M
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 18mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 12-TQFN-EP(4x4)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,雙極
MAX1070/MAX1071
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
______________________________________________________________________________________
13
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 10 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1070/MAX1071 require 16 clock cycles
from the P to clock out the 10 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
10 data bits, 2 sub-bits, and a trailing zero with the data
in MSB-first format.
DSP Interface to the TMS320C54_
The MAX1070/MAX1071 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1070/MAX1071 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
SCLK
DOUT
916
8
1
D0
D9
D8
D6
D5
D4
D3
D2
D1
D7
HIGH-Z
CNVST
S1
S0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
0
D9D8D7
D6D5
D4D3
D2D1
D0
S1
S0
0
DOUT
SCLK
CNVST
0
1
14
16
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
SCLK
DOUT
CNVST
16
S0
S1
D9
D8
D4
D5
D6
D3
D2
D1
D0
HIGH-Z
D7
HIGH-Z
2
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