參數(shù)資料
型號: MAX1071ETC-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 1.5Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs
中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC12
封裝: 4 X 4 MM, 0.80 MM HEIGHT, MO-220-WGGB, TQFN-12
文件頁數(shù): 13/18頁
文件大?。?/td> 1222K
代理商: MAX1071ETC-T
M
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
______________________________________________________________________________________
13
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 10 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1070/MAX1071 require 16 clock cycles
from the μP to clock out the 10 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
10 data bits, 2 sub-bits, and a trailing zero with the data
in MSB-first format.
DSP Interface to the TMS320C54_
The MAX1070/MAX1071 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1070/MAX1071 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
SCLK
DOUT
9
16
8
1
D0
D9
D8
D6
D5
D4
D3
D2
D1
D7
HIGH-Z
HIGH-Z
CNVST
S1
S0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
0
DOUT
SCLK
CNVST
0
1
1
14
16
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
SCLK
DOUT
CNVST
16
S0
S1
D9
D8
D4
D5
D6
D3
D2
D1
D0
HIGH-Z
D7
HIGH-Z
2
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