參數(shù)資料
型號(hào): MAX1071CTC-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 1.5Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs
中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC12
封裝: 4 X 4 MM, 0.80 MM HEIGHT, MO-220-WGGB, TQFN-12
文件頁數(shù): 4/18頁
文件大?。?/td> 1222K
代理商: MAX1071CTC-T
M
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
4
_______________________________________________________________________________________
Note 1:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2:
No missing codes over temperature.
Note 3:
Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4:
At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5:
The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNST. The IC idles in acquisition mode between conversions.
Note 6:
Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7:
1.5Msps operation guaranteed for V
L
> 2.7V. See the
Typical Operating Characteristics
section for recommended sampling
speeds for V
L
< 2.7V.
Note 8:
Digital supply current is measured with the V
IH
level equal to V
L
, and the V
IL
level equal to GND.
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +3.6V, V
L
= V
DD
, V
REF
= 2.048V, f
SCLK
= 24.0MHz, 50% duty cycle, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at V
DD
= 3V and T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
18.7
TYP
MAX
UNITS
V
L
= 2.7V to V
DD
V
L
= 1.8V to V
DD
, minimum recommended
(Note 7)
SCLK Pulse-Width High
t
CH
22.5
ns
V
L
= 2.7V to V
DD
V
L
= 1.8V to V
DD
, minimum recommended
(Note 7)
18.7
SCLK Pulse-Width Low
t
CL
22.5
ns
C
L
= 30pF, V
L
= 2.7V to V
DD
C
L
= 30pF, V
L
= 1.8V to V
DD
V
L
= 1.8V to V
DD
V
L
= 1.8V to V
DD
V
L
= 1.8V to V
DD
17
24
SCLK Rise to DOUT Transition
t
DOUT
ns
DOUT Remains Valid After SCLK
CNVST Fall to SCLK Fall
CNVST Pulse Width
Power-Up Time; Full Power-Down
Restart Time; Partial Power-Down
t
DHOLD
t
SETUP
t
CSW
t
PWR-UP
t
RCV
4
10
20
ns
ns
ns
ms
2
16
Cycles
CNVST
SCLK
DOUT
t
DHOLD
t
DOUT
t
SETUP
t
CSW
t
CL
t
CH
Figure 1. Detailed Serial-Interface Timing
GND
6k
C
L
DOUT
DOUT
C
L
GND
V
L
a) HIGH-Z TO V
OH
, V
OL
TO V
OH
,
AND V
OH
TO HIGH-Z
b) HIGH-Z TO V
OL
, V
OH
TO V
OL
,
AND V
OL
TO HIGH-Z
6k
Figure 2. Load Circuits for Enable/Disable Times
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