參數(shù)資料
型號: MAX1069ACUD
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 58.6ksps, 14-Bit, 2-Wire Serial ADC
中文描述: 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO14
封裝: TSSOP-14
文件頁數(shù): 5/20頁
文件大小: 442K
代理商: MAX1069ACUD
M
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
_______________________________________________________________________________________
5
Note 1:
DC accuracy is tested at AV
DD
= +5.0V and DV
DD
= +3.0V. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection test.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3:
Offset nullified.
Note 4:
One sample is achieved every 18 clocks in continuous conversion mode.
Note 5:
The track/hold acquisition time is two SCL cycles as illustrated in Figure 11.
Note 6:
A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
50ns in fast mode.
Note 7:
ADC performance is limited by the converter
s noise floor, typically 480μV
P-P
.
Note 8:
N
[
where N is the number of bits (
PSRR
V
(5.25V)- V
(4.75V)
2
V
5.25V - 4.75V
FS
FS
REF
=
]
×
).
14
t
2
1
f
ACQ
SCL
=
×
f
1 clocks
f
SCL
t
SAMPLE
C
-1
=
+
8
ONV
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= +4.75V to +5.25V, DV
DD
= +2.7V to +5.5V, f
SCL
= 1.7MHz (33% duty cycle), f
SAMPLE
= 58.6ksps, V
REF
= +4.096V, external ref-
erence applied to REF, REFADJ = AV
DD
, C
REF
= 10μF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.)
PARAMETER
SYM B O L
CONDITIONS
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE
(Figure 1b and Figure 2)
Serial Clock Frequency
f
SCLH
(Note 11)
Hold Time, (Repeated) Start
Condition
MIN
TYP
MAX
UNITS
1.7
MHz
t
HD,STA
160
ns
Low Period of the SCL Clock
High Period of the SCL Clock
t
LOW
t
HIGH
320
120
ns
ns
Setup Time for a Repeated
START Condition
t
SU,STA
160
ns
Data Hold Time
Data Setup Time
t
HD,DAT
t
SU,DAT
(Note 9)
0
10
150
ns
ns
Rise Time of SCL Signal
(Current Source Enabled)
t
RCL
(Note 10)
10
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
C ap aci i ve Load for E ach Bus Li ne
Pulse Width of Spike Suppressed
t
RCL1
(Note 10)
20
160
ns
t
FCL
t
RDA
t
FDA
t
SU,STO
C
B
t
SP
(Note 10)
(Note 10)
(Note 10)
20
20
20
160
80
160
160
ns
ns
ns
ns
pF
ns
400
10
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