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參數(shù)資料
| 型號： | MAX1067BEEE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | Multichannel, 14-Bit, 200ksps Analog-to-Digital Converters |
| 中文描述： | 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.150 INCH, 0.250 INCH PITCH, MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 21/30頁 |
| 文件大?。?/td> | 447K |
| 代理商： | MAX1067BEEE |
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DSP 8-Bit-Wide Data-Transfer Mode (External Clock
Mode, MAX1068 Only)
Figure 16 shows the DSP-interface timing diagram.
Logic low at DSPR on the falling edge of
CS
enables
DSP interface mode. After the MAX1068 enters DSP
mode,
CS
can remain low for the duration of the con-
version process and each subsequent conversion.
Drive DSEL low to select the 8-bit data-transfer mode.
A sync pulse from the DSP at DSPR wakes the analog
circuitry and allows SCLK to clock in data (Figure 17).
The frame sync pulse alerts the MAX1068 that incom-
ing data is about to be sent to DIN. Ensure the duty
cycle on SCLK is between 45% and 55% when operat-
ing at 4.8MHz (the maximum clock frequency). For
lower clock frequencies, ensure the minimum high and
low times are at least 93ns. External clock mode con-
versions with SCLK rates less than 125kHz can reduce
accuracy due to leakage of the sampling capacitor.
The input data latches on the falling edge of SCLK. The
command/configuration/control register starts reading
data in on the falling edge of the first SCLK cycle imme-
diately following the falling edge of the frame sync
pulse and ends on the falling edge of the 8th SCLK
cycle. The MAX1068 selects the proper channel for
conversion on the falling edge of the 3rd clock cycle
and begins acquisition. Acquisition continues until the
rising edge of the 7th clock cycle. The MAX1068 sam-
ples the input on the rising edge of the 7th clock cycle.
On the rising edge of the 8th clock cycle, the MAX1068
outputs a frame sync pulse at DSPX. The frame sync
pulse alerts the DSP that the conversion results are
about to be output at DOUT (MSB first) starting on the
rising edge of the 9th clock pulse. To read the entire
conversion results, 16 SCLK cycles are needed. Extra
clock pulses, occuring after the conversion result has
been clocked out, and prior to the next rising edge of
DSPR, cause zeros to be clocked out of DOUT. The
MAX1068 external-clock, DSP 8-bit-wide data-transfer
mode requires 24 clock cycles to complete.
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a con-
version immediately aborts the current conversion and
begins a new one. A rising edge on
CS
in the middle of
a conversion aborts the current conversion and places
the MAX1068 in shutdown.
DSP 16-Bit-Wide Data-Transfer Mode (External
Clock Mode, MAX1068 Only)
Figure 16 shows the DSP-interface timing diagram. Logic
low at DSPR on the falling edge of
CS
enables DSP inter-
face mode. After the MAX1068 enters DSP mode,
CS
can remain low for the duration of the conversion
process and each subsequent conversion. The acquisi-
tion time is extended an extra eight SCLK cycles in the
16-bit-wide data-transfer mode. Drive DSEL high to
select the 16-bit-wide data-transfer mode. A sync pulse
from the DSP at DSPR wakes the analog circuitry and
allows SCLK to clock in data (Figure 18). The frame
sync pulse also alerts the MAX1068 that incoming data
is about to be sent to DIN. Ensure the duty cycle on
SCLK is between 45% and 55% when operating at
M
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________
21
CS
SCLK
DSPR
DIN
DOUT
t
CSS
t
CL
t
DS
t
DH
t
DV
t
CH
t
DO
t
TR
t
FSH
t
CSH
t
DF
t
CP
t
CSW
t
FSS
...
...
...
...
...
Figure 16. Detailed DSP-Interface Timing (MAX1068 Only)
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1067BEEE+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC MULTICH 200KSPS ANLG-DGTL CNVTRS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1067BEEE+T | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC ADC 14BIT SRL 200KSPS 16QSOP 制造商:Maxim Integrated Products 功能描述:MULTICH 200KSPS ANLG-DGTL CNVTRS |
| MAX1067BEEE-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1067CCEE | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1067CCEE-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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