參數(shù)資料
型號(hào): MAX1064
廠商: Maxim Integrated Products, Inc.
英文描述: 400ksps. +5V. 8-/4-Channel. 10-Bit ADCs with +2.5V Reference and Parallel Interface
中文描述: 400ksps、+5V、8/4通道、10位ADC,帶有+2.5V電壓基準(zhǔn)及并行接口
文件頁(yè)數(shù): 8/20頁(yè)
文件大小: 488K
代理商: MAX1064
M
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
8
_______________________________________________________________________________________
Pin Description
NAME
FUNCTION
1
HBEN
High Byte Enable. Used to multiplex the 10-bit conversion result.
1: 2 MSBs are multiplexed on the data bus.
0: 8 LSBs are available on the data bus.
PIN
2
3
4
5
6
7
8
9
10
D7
D6
D5
D4
D3
D2
Tri-State Digital I/O Line (D7)
Tri-State Digital I/O Line (D6)
Tri-State Digital I/O Line (D5)
Tri-State Digital I/O Line (D4)
Tri-State Digital I/O Line (D3)
Tri-State Digital I/O Line (D2)
Tri-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
Tri-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
INT
goes low when the conversion is complete and the output data is ready.
D1/D9
D0/D8
INT
11
RD
Active-Low Read Select. If
CS
is low, a falling edge on
RD
enables the read operation on the
data bus.
12
WR
Active-Low Write Select. When
CS
is low in internal acquisition mode, a rising edge on
WR
latches in configuration data and starts an acquisition plus a conversion cycle. When
CS
is
low in external acquisition mode, the first rising edge on
WR
ends acquisition and starts a
conversion.
13
CLK
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock. In inter-
nal clock mode, connect this pin to either V
DD
or GND.
Active-Low Chip Select. When
CS
is high, digital outputs (D7–D0) are high impedance.
Analog Input Channel 7
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
14
15
16
17
18
19
20
21
22
CS
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
23
COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.
24
GND
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01μF
capacitor. When using an external reference, connect REFADJ to V
DD
to disable the internal
bandgap reference.
25
REFADJ
26
REF
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7μF capacitor to GND
when using the internal reference.
27
V
DD
Analog +5V Power Supply. Bypass with a 0.1μF capacitor to GND.
28
V
LOGIC
Digital Power Supply. V
LOGIC
powers the digital outputs of the data converter and can range
from +2.7V to (V
DD
+ 300mV).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MAX1060
MAX1064
相關(guān)PDF資料
PDF描述
MAX1064AEEG 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
MAX1064BCEG 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
MAX1064BEEG 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
MAX1060ACEI 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface
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