參數(shù)資料
型號: MAX1063ACEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 15/20頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 250KSPS 24-QSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 10
采樣率(每秒): 250k
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
功率耗散(最大): 762mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 24-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;4 個單端,雙極;2 個偽差分,單極;2 個偽差分,雙極
MAX1061/MAX1063
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Shutdown mode
Standby mode
Operating mode,
fSAMPLE = 250ksps
A
210
0.9
1.2
mA
2.3
2.6
V
2.7
3.6
VDD
Analog Supply Voltage
150
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
VLOGIC Current
ILOGIC
CL = 20pF
210
A
Power-Supply Rejection
PSR
VDD = 3V ±10%, full-scale input
±0.4
±0.9
mV
fSAMPLE = 250ksps
Not converting
V
1.8
VDD + 0.3
VLOGIC
Digital Supply Voltage
WR to CLK Fall Setup Time
tCWS
40
ns
CLK Pulse Width High
ns
CLK Period
tCH
40
tCP
208
CLK Pulse Width Low
tCL
40
ns
Data Valid to WR Rise Time
tDS
40
ns
WR Rise to Data Valid Hold Time
tDH
0
ns
CLK Fall to WR Hold Time
tCWH
40
ns
CS to CLK or WR
Setup Time
tCSWS
60
ns
CLK or WR to CS
Hold Time
tCSWH
0
ns
CS Pulse Width
tCS
100
ns
WR Pulse Width
tWR
60
ns
tTC
20
100
ns
(Note 8)
CLOAD = 20pF, Figure 1
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
CS Rise to Output Disable
POWER REQUIREMENTS
Internal reference
External reference
1.9
2.3
0.5
0.8
IDD
Positive Supply Current
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