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參數(shù)資料
| 型號： | MAX1061BEEI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 250KSPS 28-QSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 667mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 28-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極；4 個偽差分，單極；4 個偽差分，雙極 |
MAX1061/MAX1063
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________
15
Table 4. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
*
Channels CH4–CH7 apply to MAX1061 only.
A1
CH0
0
+
0
-
0
A0
0
-
1
CH2
CH4*
+
0
1
0
+
-
CH3
0
CH1
CH7*
CH6*
1
CH5*
1
-
+
0
A2
+
-
1
0
1
-
+
1
0
-
1
+
1
+
-
Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1061/MAX1063 in external
clock mode and sets INT high. After the power supplies
stabilize, the internal reset time is 10s, and no conver-
sions should be attempted during this phase. When
using the internal reference, 500s are required for
VREF to stabilize.
Internal and External Reference
The MAX1061/MAX1063 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
An internal buffer is designed to provide +2.5V at REF for
both the MAX1061 and the MAX1063. The internally
trimmed +1.22V reference is buffered with a +2.05V/V
gain.
Internal Reference
With the internal reference, the full-scale range is +2.5V
with unipolar inputs and ±1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
(±100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7F min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize noise on the
reference, connect a 0.01F capacitor between
REFADJ and GND.
External Reference
With both the MAX1061 and MAX1063, an external ref-
erence can be placed at either the input (REFADJ) or
the output (REF) of the internal reference buffer amplifier.
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17k.
Table 5. Data-Bus Output (8 + 2 Parallel
Interface)
UNIPOLAR
(UNI/BIP = 1)
BIPOLAR
(UNI/BIP = 0)
0
D6
D7
Bit 9
Bit 7
Bit 9
Bit 6
D2
Bit 9
Bit 2
D1
Bit 9 (MSB)
Bit 1
HBEN = 1
Bit 8
HBEN = 0
Bit 0 (LSB)
PIN
D0
VDD = +3V
330k
50k
GND
50k
0.01F
4.7F
REFADJ
REF
MAX1061
MAX1063
GND
Figure 7. Reference Voltage Adjustment with External
Potentiometer
0
D3
Bit 9
Bit 3
0
D4
Bit 9
Bit 4
0
D5
Bit 9
Bit 5
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