8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 14-Bit ADCs 19 Maxim Integrated 0" />
參數(shù)資料
型號(hào)： MAX1033BEUP+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 11/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC LP 4-CHAN 12V 20-TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 14
采樣率（每秒）： 115k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 105.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，雙極
MAX1032/MAX1033
8- and 4-Channel, ±3 x VREF
Multirange Inputs, Serial 14-Bit ADCs
19
Maxim Integrated
001
010
011
100
101
110
111
0
-3 x VREF
+3 x VREF
EACH INPUT IS FAULT TOLERANT TO
±16.5V.
VREF = 4.096V.
(CH_)
-
AGND1
(V)
INPUT RANGE SELECTION BITS, R[2:0]
(3
x
V
REF
)/2
(3
x
V
REF
)/2
(3
x
V
REF
)/2
3x
V
REF
3x
V
REF
3x
V
REF
6x
V
REF
2
-3 x VREF
2
+3 x VREF
Figure 7. Single-Ended Input Voltage Ranges
001
010
011
100
101
110
111
+6 x VREF
-6 x VREF
EACH INPUT IS FAULT TOLERANT TO
±16.5V.
VREF = 4.096V.
(CH_+)
-
(CH_-)
(V)
INPUT RANGE SELECTION BITS, R[2:0]
0
3x
V
REF
6x
V
REF
12
x
V
REF
2
+3 x VREF
2
-3 x VREF
2
+3 x VREF
2
-3 x VREF
Figure 8. Differential Input Voltage Ranges
Digital Interface
The MAX1032/MAX1033 feature a serial interface that is
compatible with SPI/QSPI and MICROWIRE devices.
DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirec-
tional communication between the MAX1032/MAX1033
and the master at SCLK rates up to 10MHz (internal
clock mode, mode 2), 3.67MHz (external clock mode,
mode 0), or 4.39MHz (external acquisition mode, mode
1). The master, typically a microcontroller, should use
the CPOL = 0, CPHA = 0, SPI transfer format, as shown
in the timing diagrams of Figures 2, 3, and 4.
The digital interface is used to:
Select single-ended or true-differential input channel
configurations
Select the unipolar or bipolar input range
Select the mode of operation:
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
Initiate conversions and read results
Data Input (DIN)
DIN configures the conversion start byte, analog input
configuration byte and mode-control byte. See Figures
2–4 and Tables 3–8. In each conversion mode, the DIN
bits must be driven low after the first byte.
Chip Select (
CS)
CS enables communication with the MAX1032/MAX1033.
When CS is low, data is clocked into the device from DIN
on the rising edge of SCLK and data is clocked out of
DOUT on the falling edge of SCLK. When CS is high,
activity on SCLK and DIN is ignored and DOUT is high
impedance allowing DOUT to be shared with other
peripherals. SSTRB is never high impedance and there-
fore cannot be shared with other peripherals.
Serial-Strobe Output (SSTRB)
As shown in Figures 3 and 4, the SSTRB transitions high
to indicate that the ADC has completed a conversion
and results are ready to be read by the master. SSTRB
remains low in the external clock mode (Figure 2) and
consequently may be left unconnected. SSTRB is dri-
ven high or low regardless of the state of CS, therefore
SSTRB cannot be shared with other peripherals.
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