參數(shù)資料
型號(hào)： MAX1031BETI+T
廠商： Maxim Integrated Products
文件頁數(shù)： 21/22頁
文件大?。?/td> 0K
描述： IC ADC 10BIT 300KSPS 28-TQFN-EP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
采樣率（每秒）： 300k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.67W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-TQFN-EP（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 16 個(gè)單端，單極；16 個(gè)單端，雙極；8 個(gè)差分，單極；8 個(gè)差分，雙極
MAX1027/MAX1029/MAX1031
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
8
_______________________________________________________________________________________
Pin Description
MAX1031
TQFN
MAX1031
QSOP
MAX1029
MAX1027
NAME
FUNCTION
2–12, 26,
27, 28
1–14
—
AIN0–13
Analog Inputs
—
1–10
—
AIN0–9
Analog Inputs
—
1–6
AIN0–5
Analog Inputs
13
15
—
REF-/AIN14
Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.
—
11
—
REF-/AIN10
Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.
—
7
REF-/AIN6
Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.
14
16
—
CNVST/
AIN15
Active-Low Conversion Start Input/Analog Input 15. See Table 3
for details on programming the setup register.
—
12
—
CNVST/
AIN11
Active-Low Conversion Start Input/Analog Input 11. See Table 3
for details on programming the setup register.
——
—
8
CNVST/
AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
15
17
13
9
REF+
Positive Reference Input. Bypass to GND with a 0.1μF capacitor.
16
18
14
10
GND
Ground
18
19
15
11
VDD
Power Input. Bypass to GND with a 0.1μF capacitor.
20
16
12
SCLK
Serial Clock Input. Clocks data in and out of the serial interface
(duty cycle must be 40% to 60%). See Table 3 for details on
programming the clock mode.
21
17
13
CS
Active-Low Chip Select Input. When
CS is low, the serial interface
is enabled. When
CS is high, DOUT is high impedance.
22
18
14
DIN
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
23
19
15
DOUT
Serial Data Output. Data is clocked out on the falling edge of
SCLK. High impedance when
CS is connected to VDD.
24
20
16
EOC
End of Conversion Output. Data is valid after
EOC pulls low.
1, 17, 19,
25
—
N.C.
No Connection. Not internally connected.
—
EP
Exposed Pad (TQFN Only). Connect EP to GND.
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