參數(shù)資料
型號: MAX1028
廠商: Maxim Integrated Products, Inc.
元件分類: ADC
英文描述: 10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference
中文描述: 10位、300ksps ADC,帶有FIFO、溫度傳感器及內(nèi)置基準(zhǔn)
文件頁數(shù): 8/24頁
文件大?。?/td> 474K
代理商: MAX1028
M
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
8
_______________________________________________________________________________________
Pin Description
MAX1030
QFN
MAX1030
QSOP
MAX1028
MAX1026
NAME
FUNCTION
1, 17, 19,
25
N.C.
No Connection. Not internally connected.
2
12, 26,
27, 28
1
14
AIN0
13
Analog Inputs
1
10
1
6
AIN0
9
AIN0
5
Analog Inputs
Analog Inputs
13
15
REF-/AIN14
Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.
11
REF-/AIN10
Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.
7
REF-/AIN6
Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.
14
16
CNVST
/
AIN15
Active-Low Conversion Start Input/Analog Input 15. See Table 3
for details on programming the setup register.
12
CNVST
/
AIN11
Active-Low Conversion Start Input/Analog Input 11. See Table 3
for details on programming the setup register.
8
CNVST
/
AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
15
16
18
17
18
19
13
14
15
9
10
11
REF+
GND
V
DD
Positive Reference Input. Bypass to GND with a 0.1μF capacitor.
Ground
Power Input. Bypass to GND with a 0.1μF capacitor.
20
20
16
12
SCLK
Serial Clock Input. Clocks data in and out of the serial interface.
(Duty cycle must be 40% to 60%.) See Table 3 for details on
programming the clock mode.
21
21
17
13
CS
Active-Low Chip-Select Input. When
CS
is low, the serial interface
is enabled. When
CS
is high, DOUT is high impedance.
22
22
18
14
DIN
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
23
23
19
15
DOUT
Serial Data Output. Data is clocked out on the falling edge of
SCLK. High impedance when
CS
is connected to V
DD
.
End of Conversion Output. Data is valid after
EOC
pulls low.
24
24
20
16
EOC
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